#
f077cab3 |
| 25-Jan-2024 |
Cong Dang <cong.dang.xn@renesas.com> |
clk: renesas: cpg-mssr: Add support for R-Car V4M
Initial CPG support for the R-Car V4M (R8A779H0).
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+rene
clk: renesas: cpg-mssr: Add support for R-Car V4M
Initial CPG support for the R-Car V4M (R8A779H0).
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/c678ef7164e3777fa91572f72e47ef385cea64b8.1706194617.git.geert+renesas@glider.be
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#
6aa17547 |
| 10-Jan-2024 |
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system
Some boards might use Linux and another OS at the same time. In such case, currently, during booting, Linux will stop necessary
clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system
Some boards might use Linux and another OS at the same time. In such case, currently, during booting, Linux will stop necessary module clocks which are not used on the Linux side, but are used by another OS.
To avoid such situation, renesas-cpg-mssr tries to find status = "reserved" devices (A), and adds CLK_IGNORE_UNUSED flag to its <&cgp CPG_MOD xxx> clock (B).
Table 2.4: Values for status property https://github.com/devicetree-org/devicetree-specification/releases/download/v0.4/devicetree-specification-v0.4.pdf
"reserved" Indicates that the device is operational, but should not be used. Typically this is used for devices that are controlled by another software component, such as platform firmware.
ex) scif5: serial@e6f30000 { ... (B) clocks = <&cpg CPG_MOD 202>, <&cpg CPG_CORE R8A7795_CLK_S3D1>, <&scif_clk>; ... (A) status = "reserved"; };
Cc: Aymeric Aillet <aymeric.aillet@iot.bzh> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Yusuke Goda <yusuke.goda.sx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/878r4ygfap.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
a96cbb14 |
| 18-Jul-2023 |
Rob Herring <robh@kernel.org> |
clk: Explicitly include correct DT includes
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that mer
clk: Explicitly include correct DT includes
The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes.
Acked-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5 Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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#
14e53669 |
| 02-Jun-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()
Use readl_poll_timeout_atomic() instead of open-coding the same operation.
As typically no retries are needed, 10 µs is a suitable tim
clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()
Use readl_poll_timeout_atomic() instead of open-coding the same operation.
As typically no retries are needed, 10 µs is a suitable timeout value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/832d29fd9aa3239ea949535309d2bdb003d40c9e.1685692810.git.geert+renesas@glider.be
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#
355a1a4b |
| 07-Mar-2023 |
Nick Alcock <nick.alcock@oracle.com> |
clk: renesas: remove MODULE_LICENSE in non-modules
Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to i
clk: renesas: remove MODULE_LICENSE in non-modules
Since commit 8b41fc4454e ("kbuild: create modules.builtin without Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations are used to identify modules. As a consequence, uses of the macro in non-modules will cause modprobe to misidentify their containing object file as a module when it is not (false positives), and modprobe might succeed rather than failing with a suitable error message.
So remove it in the files in this commit, none of which can be built as modules.
Signed-off-by: Nick Alcock <nick.alcock@oracle.com> Suggested-by: Luis Chamberlain <mcgrof@kernel.org> Cc: Luis Chamberlain <mcgrof@kernel.org> Cc: linux-modules@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: linux-renesas-soc@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
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#
75a2f973 |
| 02-Feb-2023 |
Takeshi Kihara <takeshi.kihara.df@renesas.com> |
clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H
The SRCR, SRSTCLR, MSTPCR and MSTPSR registers for R-Car V4H (R8A779G0) each have registers up to offset 0x74. Update the correspondi
clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H
The SRCR, SRSTCLR, MSTPCR and MSTPSR registers for R-Car V4H (R8A779G0) each have registers up to offset 0x74. Update the corresponding arrays.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/87a61wanfx.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
b1dec4e7 |
| 02-Feb-2023 |
Wolfram Sang <wsa+renesas@sang-engineering.com> |
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now,
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
R-Car H3 ES1.* was only available to an internal development group and needed a lot of quirks and workarounds. These become a maintenance burden now, so our development group decided to remove upstream support for this SoC. Public users only have ES2 onwards.
In addition to the ES1 specific removals, a check for it was added preventing the machine to boot further. It may otherwise inherit wrong clock settings from ES2 which could damage the hardware.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
1c052043 |
| 11-Jan-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: cpg-mssr: Remove superfluous check in resume code
When the code flow arrives at printing the error message in cpg_mssr_resume_noirq(), we know for sure that we are not running on an RZ
clk: renesas: cpg-mssr: Remove superfluous check in resume code
When the code flow arrives at printing the error message in cpg_mssr_resume_noirq(), we know for sure that we are not running on an RZ/A Soc, as the code checked for that before.
Fixes: ace342097768e35f ("clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/144a3e66d748c0c17f3524ac8fa6ece5bf5b6f1e.1673425314.git.geert+renesas@glider.be
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#
fbfd614a |
| 23-Dec-2022 |
Alexey Khoroshilov <khoroshilov@ispras.ru> |
clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed
If cpg_mssr_common_init() fails after assigning priv to global variable cpg_mssr_priv, it deallocates priv, but cpg_mssr_p
clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed
If cpg_mssr_common_init() fails after assigning priv to global variable cpg_mssr_priv, it deallocates priv, but cpg_mssr_priv keeps dangling pointer that potentially can be used later.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Fixes: 1f7db7bbf031 ("clk: renesas: cpg-mssr: Add early clock support") Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1671806417-32623-1-git-send-email-khoroshilov@ispras.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
0ab55cf1 |
| 28-Apr-2022 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: cpg-mssr: Add support for R-Car V4H
Initial CPG support for R-Car V4H (r8a779g0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/2
clk: renesas: cpg-mssr: Add support for R-Car V4H
Initial CPG support for R-Car V4H (r8a779g0).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
24aaff6a |
| 01-Dec-2021 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: cpg-mssr: Add support for R-Car S4-8
Initial CPG support for R-Car S4-8 (r8a779f0).
Inspired by patches in the BSP by LUU HOAI.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh
clk: renesas: cpg-mssr: Add support for R-Car S4-8
Initial CPG support for R-Car S4-8 (r8a779f0).
Inspired by patches in the BSP by LUU HOAI.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-10-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
470e3f0d |
| 01-Dec-2021 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG driver.
[1] h
clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver
According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG driver.
[1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20211201073308.1003945-9-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
97c8d514 |
| 17-Nov-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
of_genpd_add_provider_simple() might fail, this patch makes sure we check the return value of of_genpd_add_provider_simp
clk: renesas: cpg-mssr: propagate return value of_genpd_add_provider_simple()
of_genpd_add_provider_simple() might fail, this patch makes sure we check the return value of of_genpd_add_provider_simple() by propagating the return value to the caller of cpg_mssr_add_clk_domain().
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211117115101.28281-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
fa58e465 |
| 17-Nov-2021 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
Make sure we check the return value of pm_genpd_init() which might fail. Also add a devres action to remove the power-domain in-case the
clk: renesas: cpg-mssr: Check return value of pm_genpd_init()
Make sure we check the return value of pm_genpd_init() which might fail. Also add a devres action to remove the power-domain in-case the probe callback fails further down in the code flow.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20211117115101.28281-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
3f6ecaf1 |
| 04-May-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
Make the style of the comment block for the Software Reset Clearing Register offsets consistent with the comment blocks for the other
clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
Make the style of the comment block for the Software Reset Clearing Register offsets consistent with the comment blocks for the other register offsets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/97dde75fe3ff27b9639c59a43cddbd9d5c405d0c.1620119700.git.geert+renesas@glider.be
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#
682b108b |
| 04-May-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions
The Realtime Module Stop Control Register definitions (RMSTPCR(i)) are incorrect for i >= 8 on R-Car Gen2 and Gen3.
As these are unuse
clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions
The Realtime Module Stop Control Register definitions (RMSTPCR(i)) are incorrect for i >= 8 on R-Car Gen2 and Gen3.
As these are unused, and not planned to be used, just like the corresponding Modem Module Stop Control Register definitions (MMSTPCR()) on R-Mobile APE6 (they are intended for the software running on the Real-Time and Modem CPU cores), they can just be removed.
Reported-by: Hai Nguyen Pham <hai.pham.ud@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/2d8bc4d9806b419ebb06030d2f31b2ea1e59b1d6.1620119700.git.geert+renesas@glider.be
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#
f2fb4fe6 |
| 26-Mar-2021 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: Zero init clk_init_data
As clk_core_populate_parent_map() checks clk_init_data.num_parents first, and checks clk_init_data.parent_names[] before clk_init_data.parent_data[] and clk_ini
clk: renesas: Zero init clk_init_data
As clk_core_populate_parent_map() checks clk_init_data.num_parents first, and checks clk_init_data.parent_names[] before clk_init_data.parent_data[] and clk_init_data.parent_hws[], leaving the latter uninitialized doesn't do harm for now. However, it is better to play it safe, and initialize all clk_init_data structures to zeroes, to avoid any current and future members containing uninitialized data.
Remove a few explicit zero initializers, which are now superfluous.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20210326105434.1574796-1-geert+renesas@glider.be
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#
24ece965 |
| 26-Jan-2021 |
Lee Jones <lee.jones@linaro.org> |
clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation
Fixes the following W=1 kernel build warning(s):
drivers/clk/renesas/renesas-cpg-mssr.c:168: warning: Function para
clk: renesas: cpg-mssr: Fix formatting issues for 'smstpcr_saved's documentation
Fixes the following W=1 kernel build warning(s):
drivers/clk/renesas/renesas-cpg-mssr.c:168: warning: Function parameter or member 'smstpcr_saved' not described in 'cpg_mssr_priv'
Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210126124540.3320214-12-lee.jones@linaro.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
b5fb3b88 |
| 03-Nov-2020 |
Krzysztof Kozlowski <krzk@kernel.org> |
clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
The struct cpg_mssr_priv missed proper formatting:
drivers/clk/renesas/renesas-cpg-mssr.c:142: warning: cannot understand function
clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
The struct cpg_mssr_priv missed proper formatting:
drivers/clk/renesas/renesas-cpg-mssr.c:142: warning: cannot understand function prototype: 'struct cpg_mssr_priv '
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20201103162435.13689-7-krzk@kernel.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
17bcc803 |
| 11-Sep-2020 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: cpg-mssr: Add support for R-Car V3U
Initial support for R-Car V3U (r8a779a0), including core, module clocks, resets, and register access, because register specification differs from R-
clk: renesas: cpg-mssr: Add support for R-Car V3U
Initial support for R-Car V3U (r8a779a0), including core, module clocks, resets, and register access, because register specification differs from R-Car Gen2/3.
Inspired by patches in the BSP by LUU HOAI.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
8b652aa8 |
| 11-Sep-2020 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct
clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv
To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_priv. After that, we can remove unused macros like MSTPSR(). No behavioral changes.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
ffbf9cf3 |
| 11-Sep-2020 |
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> |
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
Geert suggested defining multiple register layout variants using an enum [1] to support further devices like R-Car V3U. So,
clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag
Geert suggested defining multiple register layout variants using an enum [1] to support further devices like R-Car V3U. So, use enum clk_reg_layout instead of a boolean .stbyctrl flag. No behavioral change.
[1] https://lore.kernel.org/linux-renesas-soc/CAMuHMdVAgN69p9FFnQdO4iHk2CHkeNaVui2Q-FOY6_BFVjQ-Nw@mail.gmail.com/
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1599810232-29035-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
c8a53fa1 |
| 07-Jul-2020 |
Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> |
clk: renesas: cpg-mssr: Add r8a774e1 support
Add support for the RZ/G2H (R8A774E1) SoC to the Renesas Clock Pulse Generator / Module Standby and Software Reset driver.
Signed-off-by: Marian-Cristia
clk: renesas: cpg-mssr: Add r8a774e1 support
Add support for the RZ/G2H (R8A774E1) SoC to the Renesas Clock Pulse Generator / Module Standby and Software Reset driver.
Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594138692-16816-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com [geert: Mark RWDT critical, cfr. commit f23f1101ad0ef1ac ("clk: renesas: rcar-gen3: Mark RWDT clocks as critical")] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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#
ed4a1180 |
| 16-Jun-2020 |
Ulrich Hecht <uli+renesas@fpond.eu> |
clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
This allows us to add the RWDT clock to the list of critical clocks without keeping it enabled needlessly if not used.
Changing th
clk: renesas: cpg-mssr: Mark clocks as critical only if on at boot
This allows us to add the RWDT clock to the list of critical clocks without keeping it enabled needlessly if not used.
Changing the semantics of crit_mod_clks in this way is safe for the current user (INTC-AP) because it is never off at boot time.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu> Link: https://lore.kernel.org/r/20200616162626.27944-2-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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ace34209 |
| 07-May-2020 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
On SoCs with Standby Control Registers (STBCRs) instead of Module Stop Control Registers (MSTPCRs), the suspend handler saves the wrong regi
clk: renesas: cpg-mssr: Fix STBCR suspend/resume handling
On SoCs with Standby Control Registers (STBCRs) instead of Module Stop Control Registers (MSTPCRs), the suspend handler saves the wrong registers, and the resume handler prints the wrong register in an error message.
Fortunately this cannot happen yet, as the suspend/resume code is used on PSCI systems only, and systems with STBCRs (RZ/A1 and RZ/A2) do not use PSCI. Still, it is better to fix this, to avoid this becoming a problem in the future.
Distinguish between STBCRs and MSTPCRs where needed. Replace the useless printing of the virtual register address in the resume error message by printing the register index.
Fixes: fde35c9c7db5732c ("clk: renesas: cpg-mssr: Add R7S9210 support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20200507074713.30113-1-geert+renesas@glider.be
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