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6f2bde9b |
| 15-Jun-2023 |
Rodrigo Siqueira <rodrigo.siqueira@amd.com> |
drm/amd/display: Add missing static
After enable DRM_AMDGPU_WERROR, clang highlight multiple functions that need to have `static`, and this commit address those issues and also improve the indents.
drm/amd/display: Add missing static
After enable DRM_AMDGPU_WERROR, clang highlight multiple functions that need to have `static`, and this commit address those issues and also improve the indents.
Reviewed-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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39a1355f |
| 06-May-2021 |
Wesley Chalmers <Wesley.Chalmers@amd.com> |
drm/amd/display: Add interface for ADD & DROP PIXEL Registers
[WHY] HW has handed down a new sequence that requires access to these registers.
v2: squash in DCN3.1 fixes (Alex)
Signed-off-by: Wesl
drm/amd/display: Add interface for ADD & DROP PIXEL Registers
[WHY] HW has handed down a new sequence that requires access to these registers.
v2: squash in DCN3.1 fixes (Alex)
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b4d56e0c |
| 06-May-2021 |
Wesley Chalmers <Wesley.Chalmers@amd.com> |
drm/amd/display: Add Interface to set FIFO ERRDET SW Override
[WHY] HW has handed down a new sequence which requires access to the FIFO ERRDET SW Override register.
Signed-off-by: Wesley Chalmers <
drm/amd/display: Add Interface to set FIFO ERRDET SW Override
[WHY] HW has handed down a new sequence which requires access to the FIFO ERRDET SW Override register.
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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880af2ea |
| 01-Nov-2020 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: cap dpp dto phase not more than modulo.
[Why] 4K monitor shows corruption if dpp dto phase is larger than modulo.
[How] cap phase value never larger than modulo.
Signed-off-by: Yo
drm/amd/display: cap dpp dto phase not more than modulo.
[Why] 4K monitor shows corruption if dpp dto phase is larger than modulo.
[How] cap phase value never larger than modulo.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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c07cbc1f |
| 26-Oct-2020 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: update dpp dto phase and modulo.
[Why & How] Program modulo with ref dpp clk Mhz/10. Program phase with pipe dpp clk Mhz /10. DMUB FW could use these value to determine optimization
drm/amd/display: update dpp dto phase and modulo.
[Why & How] Program modulo with ref dpp clk Mhz/10. Program phase with pipe dpp clk Mhz /10. DMUB FW could use these value to determine optimization clk for PSR power saving.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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