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efc1d1c9 |
| 03-Aug-2023 |
Qingqing Zhuo <Qingqing.Zhuo@amd.com> |
drm/amd/display: Update DCN31 for DCN35 support
[Why & How] Update DCN31 files for DCN35 usage.
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com
drm/amd/display: Update DCN31 for DCN35 support
[Why & How] Update DCN31 files for DCN35 usage.
Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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7af87fc1 |
| 31-Oct-2022 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Add HUBP surface flip interrupt handler
On IGT, there is a test named amd_hotplug, and when the subtest basic is executed on DCN31, we get the following error:
[drm] *ERROR* [CRTC:
drm/amd/display: Add HUBP surface flip interrupt handler
On IGT, there is a test named amd_hotplug, and when the subtest basic is executed on DCN31, we get the following error:
[drm] *ERROR* [CRTC:71:crtc-0] flip_done timed out [drm] *ERROR* flip_done timed out [drm] *ERROR* [CRTC:71:crtc-0] commit wait timed out [drm] *ERROR* flip_done timed out [drm] *ERROR* [CONNECTOR:88:DP-1] commit wait timed out [drm] *ERROR* flip_done timed out [drm] *ERROR* [PLANE:59:plane-3] commit wait timed out
After enable the page flip log with the below command:
echo -n 'format "[PFLIP]" +p' > /sys/kernel/debug/dynamic_debug/control
It is possible to see that the flip was submitted, but DC never replied back, which generates time-out issues. This is an indication that the HUBP surface flip is missing. This commit fixes this issue by adding hubp1_set_flip_int to DCN31.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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84de5c2e |
| 12-May-2022 |
Gabe Teeger <gabe.teeger@amd.com> |
drm/amd/display: Update optimized blank calc and programming
[Why] The existing calculations in DCN3.1 were placeholder and need to be replaced with HW team approved calculations.
[How] The new cal
drm/amd/display: Update optimized blank calc and programming
[Why] The existing calculations in DCN3.1 were placeholder and need to be replaced with HW team approved calculations.
[How] The new calculations add new parameters to the bounding box and pipe params - VblankNom and the bounding box default.
The placeholder calculations are dropped from DCN3.1 in the meantime while we work out hardware approved replacements. Also fix a bug where we wipe out other register contents with a REG_SET instead of a REG_UPDATE for the register we were programming the min_dst_y_next_start_optimized.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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72f05e3b |
| 21-Apr-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/display: make hubp31_program_extended_blank static
It's not used outside of dcn31_hubp.c.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deuc
drm/amdgpu/display: make hubp31_program_extended_blank static
It's not used outside of dcn31_hubp.c.
Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e5fc7825 |
| 14-Mar-2022 |
Gabe Teeger <gabe.teeger@amd.com> |
drm/amd/display: Add support for zstate during extended vblank
[why] When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank portion to enter zstate if possible.
[how] When we enter fre
drm/amd/display: Add support for zstate during extended vblank
[why] When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank portion to enter zstate if possible.
[how] When we enter freesync, a full update is triggered and the new vtotal with extra lines is passed to dml in a stream update. The time gained from extra vblank lines is calculated in microseconds. We allow zstate entry if the time gained is greater than 5 ms, which is the current policy. Furthermore, an optimized value for min_dst_y_next_start is calculated and written to its register. When exiting freesync, another full update is triggered and default values are restored.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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ba5a5371 |
| 19-May-2021 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Add DCN3.1 DCHHUB
Adds DCN3.1 DCHHUB programming and modifies DCN20/DCN30 shared hardware sequencer helpers to use these hooks.
HW Blocks:
+--------++------+ +----------+
drm/amd/display: Add DCN3.1 DCHHUB
Adds DCN3.1 DCHHUB programming and modifies DCN20/DCN30 shared hardware sequencer helpers to use these hooks.
HW Blocks:
+--------++------+ +----------+ |DCHUBBUB|| HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | <---------> | DWB | +--------+ +--------+ | ^ v | +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+
No changes to MMHUBBUB or DWB programming, added to diagram for clarity.
Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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