#
130afc8a |
| 22-Apr-2024 |
Jose Fernandez <josef@netflix.com> |
drm/amd/display: Fix division by zero in setup_dsc_config
When slice_height is 0, the division by slice_height in the calculation of the number of slices will cause a division by zero driver crash.
drm/amd/display: Fix division by zero in setup_dsc_config
When slice_height is 0, the division by slice_height in the calculation of the number of slices will cause a division by zero driver crash. This leaves the kernel in a state that requires a reboot. This patch adds a check to avoid the division by zero.
The stack trace below is for the 6.8.4 Kernel. I reproduced the issue on a Z16 Gen 2 Lenovo Thinkpad with a Apple Studio Display monitor connected via Thunderbolt. The amdgpu driver crashed with this exception when I rebooted the system with the monitor connected.
kernel: ? die (arch/x86/kernel/dumpstack.c:421 arch/x86/kernel/dumpstack.c:434 arch/x86/kernel/dumpstack.c:447) kernel: ? do_trap (arch/x86/kernel/traps.c:113 arch/x86/kernel/traps.c:154) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? do_error_trap (./arch/x86/include/asm/traps.h:58 arch/x86/kernel/traps.c:175) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? exc_divide_error (arch/x86/kernel/traps.c:194 (discriminator 2)) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: ? asm_exc_divide_error (./arch/x86/include/asm/idtentry.h:548) kernel: ? setup_dsc_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1053) amdgpu kernel: dc_dsc_compute_config (drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dc_dsc.c:1109) amdgpu
After applying this patch, the driver no longer crashes when the monitor is connected and the system is rebooted. I believe this is the same issue reported for 3113.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Jose Fernandez <josef@netflix.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3113 Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
aece2094 |
| 12-Mar-2024 |
Aric Cyr <aric.cyr@amd.com> |
drm/amd/display: Fix compiler warnings on high compiler warning levels
[why] Enabling higher compiler warning levels results in many issues that can be trivially resolved as well as some potentially
drm/amd/display: Fix compiler warnings on high compiler warning levels
[why] Enabling higher compiler warning levels results in many issues that can be trivially resolved as well as some potentially critical issues.
[how] Fix all compiler warnings found with various compilers and higher warning levels. Primarily, potentially uninitialized variables and unreachable code.
Reviewed-by: Leo Li <sunpeng.li@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c597479f |
| 04-Jan-2024 |
Leo (Hanghong) Ma <hanghong.ma@amd.com> |
drm/amd/display: Fix timing bandwidth calculation for HDMI
[Why && How] The current bandwidth calculation for timing doesn't account for certain HDMI modes overhead which leads to DSC can't be enabl
drm/amd/display: Fix timing bandwidth calculation for HDMI
[Why && How] The current bandwidth calculation for timing doesn't account for certain HDMI modes overhead which leads to DSC can't be enabled. Add support to calculate the actual bandwidth for these HDMI modes.
Reviewed-by: Chris Park <chris.park@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5290ed0a |
| 16-Nov-2023 |
Ilya Bakoulin <ilya.bakoulin@amd.com> |
drm/amd/display: Add DSC granular throughput adjustment
[Why/How] Update DSC DPCD parsing to take granular throughput adjustment into consideration.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> A
drm/amd/display: Add DSC granular throughput adjustment
[Why/How] Update DSC DPCD parsing to take granular throughput adjustment into consideration.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Ilya Bakoulin <ilya.bakoulin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8df0d7d3 |
| 18-Oct-2023 |
Fangzhi Zuo <jerry.zuo@amd.com> |
drm/amd/display: Allow 16 max_slices for DP2 DSC
Enable 12 and 16 max_slices for DP2 DSC
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Fangzhi
drm/amd/display: Allow 16 max_slices for DP2 DSC
Enable 12 and 16 max_slices for DP2 DSC
Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
63c0bf99 |
| 17-Jun-2023 |
George Shen <george.shen@amd.com> |
drm/amd/display: Add link encoding to timing BW calculation parameters
[Why] There certain cases where the timing BW is dependent on the type of link encoding in use. Thus to calculate the correct B
drm/amd/display: Add link encoding to timing BW calculation parameters
[Why] There certain cases where the timing BW is dependent on the type of link encoding in use. Thus to calculate the correct BW required for a given timing, the link encoding should be added as a parameter.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
97476418 |
| 11-Apr-2023 |
George Shen <george.shen@amd.com> |
drm/amd/display: Add stream overhead in BW calculations for 128b/132b
[Why] Current BW calculations do not account for the additional padding added for uncompressed pixel-to-symbol packing.
This re
drm/amd/display: Add stream overhead in BW calculations for 128b/132b
[Why] Current BW calculations do not account for the additional padding added for uncompressed pixel-to-symbol packing.
This results in X.Y being too low for 128b/132b SST streams in certain scenarios. If X.Y is too low, end user can observe image corruption.
[How] Add function to calculate stream overhead to timing BW calculation for 128b/132b SST cases.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Alan Liu <haoping.liu@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
48dd83c0 |
| 17-May-2023 |
Hamza Mahfooz <hamza.mahfooz@amd.com> |
drm/amd/display: drop redundant memset() in get_available_dsc_slices()
get_available_dsc_slices() returns the number of indices set, and all of the users of get_available_dsc_slices() don't cross th
drm/amd/display: drop redundant memset() in get_available_dsc_slices()
get_available_dsc_slices() returns the number of indices set, and all of the users of get_available_dsc_slices() don't cross the returned bound when iterating over available_slices[]. So, the memset() in get_available_dsc_slices() is redundant and can be dropped.
Fixes: 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") Reported-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
6bfe9a23 |
| 30-Mar-2023 |
Nasir Osman <nasir.osman@amd.com> |
drm/amd/display: DSC policy override when ODM combine is forced
[why] When we force ODM combine with DSC, we lose several 8 bit and 10 bit modes in validation and thus not able to use HDR. This is d
drm/amd/display: DSC policy override when ODM combine is forced
[why] When we force ODM combine with DSC, we lose several 8 bit and 10 bit modes in validation and thus not able to use HDR. This is due to the number of horizontal slices used in DSC not properly being accounted for currently when 2:1 ODM Combine is forced.
[how] Enforce at least two horizontal slices are used for DSC when ODM combine is forced.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Nasir Osman <nasir.osman@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
98ce7d32 |
| 23-Feb-2023 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: convert link.h functions to function pointer style
[Why & How] All dc subcomponents should call another dc component via function pointers stored in a component structure. This is p
drm/amd/display: convert link.h functions to function pointer style
[Why & How] All dc subcomponents should call another dc component via function pointers stored in a component structure. This is part of dc coding convention since the beginning. The reason behind this is to improve encapsulation and polymorphism. The function contract is extracted into a single link service structure defined in link.h header file and implemented only in link_factory.c instead of spreading across multiple files in link component file structure.
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ab487ea8 |
| 20-Feb-2023 |
Mike Hsieh <Mike.Hsieh@amd.com> |
drm/amd/display: fix typo in dc_dsc_config_options structure
[WHY] There is a typo in dc_dsc_config_options structure
[HOW] Fix the typo
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Qi
drm/amd/display: fix typo in dc_dsc_config_options structure
[WHY] There is a typo in dc_dsc_config_options structure
[HOW] Fix the typo
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
de534c1c |
| 10-Jan-2023 |
Mike Hsieh <Mike.Hsieh@amd.com> |
drm/amd/display: Add height granularity limitation for dsc slice height calculation
[WHY] eDP add new limitation for Y granularity for selected update feature. DSC does not include this limitation w
drm/amd/display: Add height granularity limitation for dsc slice height calculation
[WHY] eDP add new limitation for Y granularity for selected update feature. DSC does not include this limitation while calculating slice height.
[HOW] Add new limitation while looking for DSC slice height.
Reviewed-by: Cruise Hung <Cruise.Hung@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
faf26f2b |
| 26-May-2022 |
pengfuyuan <pengfuyuan@kylinos.cn> |
drm/amd: Fix spelling typo in comments
Fix spelling typo in comments.
Reported-by: k2ci <kernel-bot@kylinos.cn> Signed-off-by: pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by: Alex Deucher <alexan
drm/amd: Fix spelling typo in comments
Fix spelling typo in comments.
Reported-by: k2ci <kernel-bot@kylinos.cn> Signed-off-by: pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2a64b147 |
| 21-Apr-2022 |
Thomas Zimmermann <tzimmermann@suse.de> |
drm/display: Move DSC header and helpers into display-helper module
DSC is the Display Stream Compression standard for DisplayPort. Move the DSC code into display/ and split the header into files fo
drm/display: Move DSC header and helpers into display-helper module
DSC is the Display Stream Compression standard for DisplayPort. Move the DSC code into display/ and split the header into files for protocol core and DRM helpers. Adapt all users of the code. No functional changes.
To avoid the proliferation of Kconfig options, DSC is part of DRM's support for DisplayPort. If necessary, a new option could make DSC an independent feature.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220421073108.19226-6-tzimmermann@suse.de
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#
da68386d |
| 21-Apr-2022 |
Thomas Zimmermann <tzimmermann@suse.de> |
drm: Rename dp/ to display/
Rename dp/ to display/ to account for additional display-related helpers, such as HDMI. Update all related include statements. No functional changes.
Various drivers, su
drm: Rename dp/ to display/
Rename dp/ to display/ to account for additional display-related helpers, such as HDMI. Update all related include statements. No functional changes.
Various drivers, such as i915 and amdgpu, use similar naming scheme by putting code for video-output standards into a local display/ directory. The new directory's name is aligned with this convention.
v2: * update commit message (Javier)
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220421073108.19226-3-tzimmermann@suse.de
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#
862a876c |
| 15-Mar-2022 |
Chris Park <Chris.Park@amd.com> |
drm/amd/display: Correct Slice reset calculation
[Why] Once DSC slice cannot fit pixel clock, we incorrectly reset min slices to 0 and allow max slice to operate, even when max slice itself cannot f
drm/amd/display: Correct Slice reset calculation
[Why] Once DSC slice cannot fit pixel clock, we incorrectly reset min slices to 0 and allow max slice to operate, even when max slice itself cannot fit the pixel clock properly.
[How] Change the sequence such that we correctly determine DSC is not possible when both min slices and max slices cannot fit pixel clock per slice.
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chris Park <Chris.Park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5b529e8d |
| 14-Jan-2022 |
Thomas Zimmermann <tzimmermann@suse.de> |
drm/dp: Move public DisplayPort headers into dp/
Move all public DisplayPort headers into dp/ and update users. No functional changes.
v3: * rebased onto latest drm-tip
Signed-off-by: Thomas Zimm
drm/dp: Move public DisplayPort headers into dp/
Move all public DisplayPort headers into dp/ and update users. No functional changes.
v3: * rebased onto latest drm-tip
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Daniel Vetter <daniel@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20220114114535.29157-5-tzimmermann@suse.de
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#
2665f63a |
| 20-Oct-2021 |
Mikita Lipski <mikita.lipski@amd.com> |
drm/amd/display: Enable DSC over eDP
[why] - Adding a DM interface to enable DSC over eDP on Linux - DSC over eDP will allow to power savings by reducing the bandwidth required to support panel's mo
drm/amd/display: Enable DSC over eDP
[why] - Adding a DM interface to enable DSC over eDP on Linux - DSC over eDP will allow to power savings by reducing the bandwidth required to support panel's modes - Apply link optimization algorithm to reduce link bandwidth when DSC is enabled
[how] - Read eDP panel's DSC capabilities - Apply DSC policy on eDP panel based on its DSC capabilities - Enable DSC encoder's on the pipe - Enable DSC on panel's side by setting DSC_ENABLE DPCD register - Adding link optimization algorithm to reduce link rate or lane count based
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
095041db |
| 04-Nov-2021 |
Chris Park <Chris.Park@amd.com> |
drm/amd/display: Fix Coverity Issues
[Why] Coverity discovers holes in logic that needs to be addressed for improved code integrity.
[How] Address issues found by coverity without changing the actu
drm/amd/display: Fix Coverity Issues
[Why] Coverity discovers holes in logic that needs to be addressed for improved code integrity.
[How] Address issues found by coverity without changing the actual logic.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Chris Park <Chris.Park@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e0d09634 |
| 09-Aug-2021 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: move bpp range decision in decide dsc bw range function
[why] Before get dsc bw range is used to compute DSC bw range based on the given fixed bpp min/max input. The new change will
drm/amd/display: move bpp range decision in decide dsc bw range function
[why] Before get dsc bw range is used to compute DSC bw range based on the given fixed bpp min/max input. The new change will merge any specs, signal, timing specific bpp range decision into this function. So the function needs to make a decision with all aspects considered.
Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b25715a0 |
| 09-Aug-2021 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: expose dsc overhead bw in dc dsc header
[why] DM needs to know how much overhead is added to DSC as result of AMD internal DSC limitation.
Acked-by: Mikita Lipski <mikita.lipski@am
drm/amd/display: expose dsc overhead bw in dc dsc header
[why] DM needs to know how much overhead is added to DSC as result of AMD internal DSC limitation.
Acked-by: Mikita Lipski <mikita.lipski@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: George Shen <george.shen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
91a9ead0 |
| 28-Jun-2021 |
Mark Morra <MarkAlbert.Morra@amd.com> |
drm/amd/display: Fixed EdidUtility build errors
[HOW] Added #ifdefs and refactored various parts of dc to allow dc_link to be built by AMD EDID UTILITY
[WHY] dc_dsc was refactored moving some of th
drm/amd/display: Fixed EdidUtility build errors
[HOW] Added #ifdefs and refactored various parts of dc to allow dc_link to be built by AMD EDID UTILITY
[WHY] dc_dsc was refactored moving some of the code that AMD EDID UTILITY needed to dc_link, so now dc_link needs to be included by AMD EDID UTILITY
Squash in DCN config fix (Alex)
Reviewed-by: Leung Martin <Martin.Leung@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Mark Morra <MarkAlbert.Morra@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
df0a271c |
| 22-Apr-2021 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: add dsc stream overhead for dp only
[why] Based on hardware team recommendation this additional dsc overhead is only required for DP DSC.
[how] Add a check for is_dp and only apply
drm/amd/display: add dsc stream overhead for dp only
[why] Based on hardware team recommendation this additional dsc overhead is only required for DP DSC.
[how] Add a check for is_dp and only apply the overhead if this flag is set.
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Wayne Lin <Wayne.Lin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
642d3a2b |
| 09-Apr-2021 |
Wenjing Liu <wenjing.liu@amd.com> |
drm/amd/display: take max dsc stream bandwidth overhead into account
[why] As hardware team suggested that we need to add a max dsc bw overhead into existing stream bandwidth when DSC is used. The f
drm/amd/display: take max dsc stream bandwidth overhead into account
[why] As hardware team suggested that we need to add a max dsc bw overhead into existing stream bandwidth when DSC is used. The formula as below:
max_dsc_bw_overhead = v_addressable * slice_count * 256 bit * pixel clock / v_total / h_total
effective stream bandwidth = pixel clock * bpp
stream bandwidth = effective stream bandwidth + dsc stream overhead
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Wayne Lin <waynelin@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
8c2f14c3 |
| 04-Mar-2021 |
Dillon Varone <dillon.varone@amd.com> |
drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations
[Why?] Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses redundant function now found in dc to
drm/amd/display: Add changes for dsc bpp in 16ths and unify bw calculations
[Why?] Some code still expected bpp to be used in whole bits, not 16ths. dsc.c uses redundant function now found in dc to calculate stream bandwidth from timing.
[How?] Fix code to work with 16ths instead of whole bits for dsc bpp. Refactor get_dsc_bandwidth to accept inputs in 16ths of a bit. Use dc function to calculate bandwidth from timing, and make dsc bw calculation a part of dsc.c.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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