#
c7b33856 |
| 24-Jan-2024 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
drm/amd/display: Drop some unnecessary guards
Some of the CONFIG_DRM_AMD_DC_FP was added in some non-related FPU code, which may cause confusion. This commit dropped some of the unnecessary guards.
drm/amd/display: Drop some unnecessary guards
Some of the CONFIG_DRM_AMD_DC_FP was added in some non-related FPU code, which may cause confusion. This commit dropped some of the unnecessary guards.
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
ee0a54a6 |
| 22-Jan-2024 |
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> |
Documentation/gpu: Add basic page for HUBP
Create the HUBP documentation page and add the doc references to extract the HUBP code documentation.
Cc: Mario Limonciello <mario.limonciello@amd.com> Cc
Documentation/gpu: Add basic page for HUBP
Create the HUBP documentation page and add the doc references to extract the HUBP code documentation.
Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4ed79308 |
| 15-Mar-2023 |
Alvin Lee <Alvin.Lee2@amd.com> |
drm/amd/display: Use per pipe P-State force for FPO
[Description] * Pass in pipe index for FPO cmd to DMCUB - This change will pass in the pipe index for each stream that is using FPO - This chan
drm/amd/display: Use per pipe P-State force for FPO
[Description] * Pass in pipe index for FPO cmd to DMCUB - This change will pass in the pipe index for each stream that is using FPO - This change is in preparation to enable FPO + VActive
* Use per pipe P-State force for FPO - For FPO, instead of using max watermarks value for P-State disallow, use per pipe p-state force instead - This is in preparation to enable FPO + VActive
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4652ae7a |
| 14-Feb-2023 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/display: Rename DCN config to FP
[Why & How] The only reason we have the DCN config is for floating point support. Rename it to make that clear and (hopefully) avoid misuse of the config in
drm/amd/display: Rename DCN config to FP
[Why & How] The only reason we have the DCN config is for floating point support. Rename it to make that clear and (hopefully) avoid misuse of the config in the future.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b73353f7 |
| 02-Oct-2022 |
Max Tseng <Max.Tseng@amd.com> |
drm/amd/display: Use the same cursor info across features
Since different features would need to update cursor registers, However, they would use different approaches.
To unify varied methods, this
drm/amd/display: Use the same cursor info across features
Since different features would need to update cursor registers, However, they would use different approaches.
To unify varied methods, this refactor is implemented the same update cursor info method for current varied features.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Max Tseng <Max.Tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4074f96d |
| 28-Jun-2022 |
Chris Park <chris.park@amd.com> |
drm/amd/display: Cache cursor when cursor exceeds 64x64
[Why] When Static screen from MALL, the cursor needs to be cached if cursor exceeds 64x64 size.
[How] Program the bit that cache cursor in MA
drm/amd/display: Cache cursor when cursor exceeds 64x64
[Why] When Static screen from MALL, the cursor needs to be cached if cursor exceeds 64x64 size.
[How] Program the bit that cache cursor in MALL when size of the cursor exceeds 64x64.
Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chris Park <chris.park@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1b0da5a3 |
| 04-May-2022 |
David Zhang <dingchen.zhang@amd.com> |
drm/amd/display: update cursor position to DMUB FW
[why] To involve the cursor position into dirty rectangle calculation.
[how] - separate plane and cursor update by different DMUB command - send t
drm/amd/display: update cursor position to DMUB FW
[why] To involve the cursor position into dirty rectangle calculation.
[how] - separate plane and cursor update by different DMUB command - send the cursor information while cursor updating, when updating cursor position/attribute, store cursor pos/attr to hubp, and notify dmub FW to exit psr before program cursor registers
Signed-off-by: David Zhang <dingchen.zhang@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d3dfceb5 |
| 23-Feb-2022 |
Aurabindo Pillai <aurabindo.pillai@amd.com> |
drm/amd/display: Add dependant changes for DCN32/321
[Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree
v2: squash in updates (Alex)
Signed-off-by: Aura
drm/amd/display: Add dependant changes for DCN32/321
[Why&How] This patch adds necessary changes needed in DC files outside DCN32/321 specific tree
v2: squash in updates (Alex)
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e5fc7825 |
| 14-Mar-2022 |
Gabe Teeger <gabe.teeger@amd.com> |
drm/amd/display: Add support for zstate during extended vblank
[why] When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank portion to enter zstate if possible.
[how] When we enter fre
drm/amd/display: Add support for zstate during extended vblank
[why] When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank portion to enter zstate if possible.
[how] When we enter freesync, a full update is triggered and the new vtotal with extra lines is passed to dml in a stream update. The time gained from extra vblank lines is calculated in microseconds. We allow zstate entry if the time gained is greater than 5 ms, which is the current policy. Furthermore, an optimized value for min_dst_y_next_start is calculated and written to its register. When exiting freesync, another full update is triggered and default values are restored.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
dd15640b |
| 10-Mar-2022 |
Becle Lee <becle.lee@amd.com> |
drm/amd/display: Wait for hubp read line for Pollock
[Why] Underflow occurred while hubp ret pipe read is idle and the second pipe is powered up and added. Flickering and underflow are only observed
drm/amd/display: Wait for hubp read line for Pollock
[Why] Underflow occurred while hubp ret pipe read is idle and the second pipe is powered up and added. Flickering and underflow are only observed on Pollock.
[How] Check the hubp ret pipe read prior to unlock pipes.
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by: Becle Lee <becle.lee@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
4866b0bf |
| 10-Dec-2021 |
Martin Leung <Martin.Leung@amd.com> |
drm/amd/display: implement dc_mode_memclk
why: Need interface to lower clocks when in dc (power save) mode. Must be able to work with p_state unsupported cases Can cause flicker when OS notifies us
drm/amd/display: implement dc_mode_memclk
why: Need interface to lower clocks when in dc (power save) mode. Must be able to work with p_state unsupported cases Can cause flicker when OS notifies us of dc state change
how: added dal3 interface for KMD added pathway to query smu for this softmax added blank before clock change to override underflow added logic to change clk based on pstatesupport and softmax added logic in prepare/optimize_bw to conform while changing clocks
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Pavle Kotarac <Pavle.Kotarac@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Martin Leung <Martin.Leung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
482812d5 |
| 13-Mar-2021 |
Wesley Chalmers <Wesley.Chalmers@amd.com> |
drm/amd/display: Set max TTU on DPG enable
[WHY] There is a bug in HW that causes P-State to hang when DPG is enabled in certain conditions.
[HOW] The solution is to force MIN_TTU_VBLANK register t
drm/amd/display: Set max TTU on DPG enable
[WHY] There is a bug in HW that causes P-State to hang when DPG is enabled in certain conditions.
[HOW] The solution is to force MIN_TTU_VBLANK register to maximum value whenever DPG has been enabled. Make stream do a full update on test pattern change, so that the TTUs get updated. When DPG is enabled, update the ttu_regs.min_ttu_vblank field of each pipe in the stream's topology to the maximum value (0xffffff).
v2: squash in build fix for when DCN is not defined (Alex)
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Anson Jacob <Anson.Jacob@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
7afa0033 |
| 19-Feb-2021 |
Qingqing Zhuo <qingqing.zhuo@amd.com> |
drm/amd/display: Enable pflip interrupt upon pipe enable
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP complianc
drm/amd/display: Enable pflip interrupt upon pipe enable
[Why] pflip interrupt would not be enabled promptly if a pipe is disabled and re-enabled, causing flip_done timeout error during DP compliance tests
[How] Enable pflip interrupt upon pipe enablement
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Eryk Brol <eryk.brol@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2da94e28 |
| 07-Dec-2020 |
Wesley Chalmers <Wesley.Chalmers@amd.com> |
drm/amd/display: Interfaces for hubp blank and soft reset
[WHY] HUBP blanking sequence on DCN30 requires us to check if HUBP is in blank and also toggle HUBP_DISABLE, which should instead be called
drm/amd/display: Interfaces for hubp blank and soft reset
[WHY] HUBP blanking sequence on DCN30 requires us to check if HUBP is in blank and also toggle HUBP_DISABLE, which should instead be called HUBP_SOFT_RESET for what it does in HW.
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
20f2ffe5 |
| 02-Nov-2020 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
Avoids confusion in configurations.
v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code
Reviewed
drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)
Avoids confusion in configurations.
v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> (v1) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
3a83e4e6 |
| 29-Sep-2020 |
Roman Li <Roman.Li@amd.com> |
drm/amd/display: Add dcn3.01 support to DC (v2)
Update dc for vangogh support.
v2: fix compilation without DCN 301 set.
Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alex
drm/amd/display: Add dcn3.01 support to DC (v2)
Update dc for vangogh support.
v2: fix compilation without DCN 301 set.
Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
db7b0216 |
| 21-May-2020 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Add DCN3 HUBP
Add support to program the DCN3 HUBP (Display to data fabric interface pipe)
HW Blocks:
+--------++------+ | HUBBUB || HUBP | +--------++------+ |
drm/amd/display: Add DCN3 HUBP
Add support to program the DCN3 HUBP (Display to data fabric interface pipe)
HW Blocks:
+--------++------+ | HUBBUB || HUBP | +--------++------+ | v +--------+ | DPP | +--------+ | v +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
429b9db8 |
| 08-May-2020 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Remove nv12 work around
[Why] dal side nv12 wa has a lot of side effects. KMD side wa is used, so this should be remove.
[How] Removed wa from dal side.
Signed-off-by: Yongqiang S
drm/amd/display: Remove nv12 work around
[Why] dal side nv12 wa has a lot of side effects. KMD side wa is used, so this should be remove.
[How] Removed wa from dal side.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
bae9c49b |
| 18-Dec-2019 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Only program surface flip for video plane via dmcub
Only need to do surface flip for video plane via dmcub.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony C
drm/amd/display: Only program surface flip for video plane via dmcub
Only need to do surface flip for video plane via dmcub.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
cf27a6d1 |
| 18-Nov-2019 |
Eric Yang <Eric.Yang2@amd.com> |
drm/amd/display: update chroma viewport wa
[Why] Need previously implemented chroma vp wa to work for rotation cases.
[How] Implement rotation specific wa.
Signed-off-by: Eric Yang <Eric.Yang2@amd
drm/amd/display: update chroma viewport wa
[Why] Need previously implemented chroma vp wa to work for rotation cases.
[How] Implement rotation specific wa.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1ba2a483 |
| 10-Nov-2019 |
Michael Strauss <michael.strauss@amd.com> |
drm/amd/display: Disable chroma viewport w/a when rotated 180 degrees
[WHY] Previous Renoir chroma viewport workaround fixed an MPO flicker by increasing the chroma viewport size. However, when the
drm/amd/display: Disable chroma viewport w/a when rotated 180 degrees
[WHY] Previous Renoir chroma viewport workaround fixed an MPO flicker by increasing the chroma viewport size. However, when the MPO plane is rotated 180 degrees, the viewport is read in reverse. Since the workaround increases viewport size, when reading in reverse it causes a vertical chroma offset.
[HOW] Pass rotation value to viewport set functions Temporarily disable the chroma viewport w/a when hubp is rotated 180 degrees
Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
b9fe5151 |
| 31-Oct-2019 |
Jaehyun Chung <jaehyun.chung@amd.com> |
drm/amd/display: DML Validation Dump/Check with Logging
[Why] Need validation that we are programming the expected values (rq, ttu, dlg) from DML. This debug feature will output logs if we are progr
drm/amd/display: DML Validation Dump/Check with Logging
[Why] Need validation that we are programming the expected values (rq, ttu, dlg) from DML. This debug feature will output logs if we are programming incorrect values and may help differentiate DAL issues from HW issues.
[How] Dump relevant registers for each pipe with active stream. Compare current reg values with the converted DML output. Log mismatches when found.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
1da37801 |
| 06-Nov-2019 |
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> |
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED
[Why]
DCN2 and DSC are stable enough to be build by default. So drop the flags.
[How]
Remove them using the unifdef tool. The foll
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED
[Why]
DCN2 and DSC are stable enough to be build by default. So drop the flags.
[How]
Remove them using the unifdef tool. The following commands were executed in sequence:
$ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';'
In addition:
* Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init()
Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
2c58cc6d |
| 22-Jul-2019 |
Ilya Bakoulin <Ilya.Bakoulin@amd.com> |
drm/amd/display: HUBP/HUBBUB register programming fixes
[Why] - Need to change interface function signature / add an enum to reflect the available register field values
[How] - Add a new enum and
drm/amd/display: HUBP/HUBBUB register programming fixes
[Why] - Need to change interface function signature / add an enum to reflect the available register field values
[How] - Add a new enum and modify existing functions to use it instead of bool
Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
5fc43055 |
| 15-Jul-2019 |
Julian Parkin <julian.parkin@amd.com> |
drm/amd/display: Remove duplicate interface for programming FB
[Why] There are currently two interfaces for exactly the same thing: hupb_update_dchub in hupb and update_dchub in hubbub. The hubbub v
drm/amd/display: Remove duplicate interface for programming FB
[Why] There are currently two interfaces for exactly the same thing: hupb_update_dchub in hupb and update_dchub in hubbub. The hubbub version is currently unused past dcn10, largely because the call from the dcn10 hardware sequencer does not call through the interface, so the hupb interface was used instead. This is confusing because of the duplicate code, the unused functions, and the fact that more that one block currently owns this set of registers.
[How] Remove the hubp interface entirely, as well as the register declarations that are not longer needed because of this. Change the call site to always call the hubbub version through the interface. Fix the update_dchub function in dcn20_hubbub.c to program the correct registers for dcn20.
Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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