Revision tags: v5.18-rc6, v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2 |
|
#
5f2c1192 |
| 23-Jan-2022 |
Roy Chan <roy.chan@amd.com> |
drm/amd/display: Support synchronized indirect reg access
[Why] indirect register index/data pair may be used by multi-threads. when it happens, it would cause register access issue that is hard to
drm/amd/display: Support synchronized indirect reg access
[Why] indirect register index/data pair may be used by multi-threads. when it happens, it would cause register access issue that is hard to trace.
[How] Using cgs service, which provide a sync indirect reg access api.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Roy Chan <roy.chan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.18-rc6, v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2 |
|
#
5f2c1192 |
| 23-Jan-2022 |
Roy Chan <roy.chan@amd.com> |
drm/amd/display: Support synchronized indirect reg access
[Why] indirect register index/data pair may be used by multi-threads. when it happens, it would cause register access issue that is hard to
drm/amd/display: Support synchronized indirect reg access
[Why] indirect register index/data pair may be used by multi-threads. when it happens, it would cause register access issue that is hard to trace.
[How] Using cgs service, which provide a sync indirect reg access api.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Roy Chan <roy.chan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.17-rc1, v5.16, v5.16-rc8, v5.16-rc7, v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4, v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6, v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1-dontuse, v5.11, v5.11-rc7, v5.11-rc6, v5.11-rc5, v5.11-rc4, v5.11-rc3, v5.11-rc2, v5.11-rc1, v5.10, v5.10-rc7, v5.10-rc6, v5.10-rc5, v5.10-rc4, v5.10-rc3, v5.10-rc2, v5.10-rc1, v5.9, v5.9-rc8, v5.9-rc7, v5.9-rc6, v5.9-rc5, v5.9-rc4, v5.9-rc3, v5.9-rc2, v5.9-rc1, v5.8, v5.8-rc7, v5.8-rc6, v5.8-rc5, v5.8-rc4, v5.8-rc3, v5.8-rc2, v5.8-rc1, v5.7, v5.7-rc7, v5.7-rc6, v5.7-rc5, v5.7-rc4, v5.7-rc3, v5.7-rc2, v5.7-rc1, v5.6, v5.6-rc7, v5.6-rc6, v5.6-rc5, v5.6-rc4, v5.6-rc3, v5.6-rc2, v5.6-rc1, v5.5, v5.5-rc7, v5.5-rc6, v5.5-rc5, v5.5-rc4, v5.5-rc3 |
|
#
c1e34175 |
| 17-Dec-2019 |
Noah Abradjian <noah.abradjian@amd.com> |
drm/amd/display: Indirect reg read macro with shift and mask
[Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to man
drm/amd/display: Indirect reg read macro with shift and mask
[Why] Recent double buffering changes for dcn2 use IX_REG_READ. However, this macro returns the full register value, with the need to manually shift and mask it to retrieve field data.
[How] Create new IX_REG_GET macro that handles shift and mask. Use this for double buffering reads instead of IX_REG_READ.
Signed-off-by: Noah Abradjian <noah.abradjian@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.5-rc2, v5.5-rc1, v5.4, v5.4-rc8, v5.4-rc7, v5.4-rc6 |
|
#
2200eb9e |
| 28-Oct-2019 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards
[Why] Support for DMUB only depends on support for DC. It doesn't use floating point so we don't need to guard it by any specific DCN revision.
[
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DMUB guards
[Why] Support for DMUB only depends on support for DC. It doesn't use floating point so we don't need to guard it by any specific DCN revision.
[How] Drop the guards and cleanup the newlines around each one.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.4-rc5 |
|
#
3a1627b0 |
| 25-Oct-2019 |
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> |
drm/amd/display: Add DMUB support to DC
DC will use DMUB for command submission and flow control during initialization.
Register offloading as well as submitting some BIOS commands are part of the
drm/amd/display: Add DMUB support to DC
DC will use DMUB for command submission and flow control during initialization.
Register offloading as well as submitting some BIOS commands are part of the DC internal interface but are guarded behind debug options.
It won't be functional in amdgpu_dm yet since we don't pass the DMUB service to DC for use.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.4-rc4, v5.4-rc3, v5.4-rc2, v5.4-rc1, v5.3, v5.3-rc8, v5.3-rc7, v5.3-rc6, v5.3-rc5, v5.3-rc4, v5.3-rc3, v5.3-rc2, v5.3-rc1, v5.2, v5.2-rc7, v5.2-rc6, v5.2-rc5, v5.2-rc4, v5.2-rc3, v5.2-rc2, v5.2-rc1, v5.1, v5.1-rc7, v5.1-rc6, v5.1-rc5, v5.1-rc4, v5.1-rc3, v5.1-rc2, v5.1-rc1, v5.0, v5.0-rc8, v5.0-rc7 |
|
#
30eb85ff |
| 15-Feb-2019 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Combine field toggle macro and sequence write macro.
[Why] field toggle write is actual field sequence write with the same field name.
[How] Use REG_UPDATE_SEQ_2 for both sequence
drm/amd/display: Combine field toggle macro and sequence write macro.
[Why] field toggle write is actual field sequence write with the same field name.
[How] Use REG_UPDATE_SEQ_2 for both sequence write and toggle. Rename REG_UPDATE_1by1_3 to REG_UPDATE_SEQ_3.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
148cccf2 |
| 13-Feb-2019 |
Yongqiang Sun <yongqiang.sun@amd.com> |
drm/amd/display: Refactor reg_set and reg_update.
[Why] Current reg update and reg set use same functions and only delta is update reads reg value and call update function.
[How] Refactor reg updat
drm/amd/display: Refactor reg_set and reg_update.
[Why] Current reg update and reg set use same functions and only delta is update reads reg value and call update function.
[How] Refactor reg update and reg set functions. 1.Implement different functions for reg update and reg set. 2.Wrap same process to a help function, both reg update and reg set will call it.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v5.0-rc6, v5.0-rc5, v5.0-rc4, v5.0-rc3, v5.0-rc2, v5.0-rc1, v4.20, v4.20-rc7, v4.20-rc6, v4.20-rc5, v4.20-rc4, v4.20-rc3, v4.20-rc2, v4.20-rc1, v4.19, v4.19-rc8, v4.19-rc7, v4.19-rc6, v4.19-rc5, v4.19-rc4, v4.19-rc3, v4.19-rc2, v4.19-rc1, v4.18, v4.18-rc8, v4.18-rc7, v4.18-rc6, v4.18-rc5, v4.18-rc4, v4.18-rc3, v4.18-rc2 |
|
#
16aecfd4 |
| 16-Jun-2018 |
Tony Cheng <tony.cheng@amd.com> |
drm/amd/display: generic indirect register access
add generic indirect register access following our register access pattern
this will make it easier to review code and programming sequence, with a
drm/amd/display: generic indirect register access
add generic indirect register access following our register access pattern
this will make it easier to review code and programming sequence, with all the complexity hidden in macro
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v4.18-rc1, v4.17, v4.17-rc7, v4.17-rc6, v4.17-rc5, v4.17-rc4, v4.17-rc3, v4.17-rc2, v4.17-rc1, v4.16 |
|
#
0a93dc7f |
| 29-Mar-2018 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: add rq/dlg/ttu to dtn log
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry
drm/amd/display: add rq/dlg/ttu to dtn log
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v4.16-rc7, v4.16-rc6, v4.16-rc5, v4.16-rc4, v4.16-rc3, v4.16-rc2, v4.16-rc1, v4.15, v4.15-rc9, v4.15-rc8, v4.15-rc7, v4.15-rc6, v4.15-rc5, v4.15-rc4, v4.15-rc3, v4.15-rc2, v4.15-rc1, v4.14, v4.14-rc8, v4.14-rc7, v4.14-rc6, v4.14-rc5, v4.14-rc4, v4.14-rc3, v4.14-rc2, v4.14-rc1, v4.13, v4.13-rc7, v4.13-rc6, v4.13-rc5, v4.13-rc4, v4.13-rc3, v4.13-rc2, v4.13-rc1 |
|
#
daf6b57d |
| 11-Jul-2017 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: add line number to reg_wait timeout print
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry
drm/amd/display: add line number to reg_wait timeout print
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
184debdb |
| 05-Jul-2017 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: refactor dcn10 hw_sequencer to new reg access style
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentl
drm/amd/display: refactor dcn10 hw_sequencer to new reg access style
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v4.12, v4.12-rc7, v4.12-rc6, v4.12-rc5, v4.12-rc4, v4.12-rc3, v4.12-rc2, v4.12-rc1, v4.11 |
|
#
50db413d |
| 24-Apr-2017 |
Tony Cheng <tony.cheng@amd.com> |
drm/amd/display: clarify delay param for REG_WAIT
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin
drm/amd/display: clarify delay param for REG_WAIT
Signed-off-by: Tony Cheng <tony.cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v4.11-rc8, v4.11-rc7, v4.11-rc6, v4.11-rc5, v4.11-rc4, v4.11-rc3, v4.11-rc2, v4.11-rc1, v4.10, v4.10-rc8, v4.10-rc7, v4.10-rc6, v4.10-rc5, v4.10-rc4, v4.10-rc3, v4.10-rc2, v4.10-rc1 |
|
#
cb9a5a90 |
| 15-Dec-2016 |
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> |
drm/amd/display: define reg helpers to update registers with 8 and 9 fields
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harr
drm/amd/display: define reg helpers to update registers with 8 and 9 fields
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
98d2cc2b |
| 12-Dec-2016 |
Andrew Wong <andrew.wong1@amd.com> |
drm/amd/display: Change locking of registers when flipping frames.
- Introduce GRPH_UPDATE_LOCK around programming surface flip. - Remove the now unused graphic surface lock. - Add macros to get and
drm/amd/display: Change locking of registers when flipping frames.
- Introduce GRPH_UPDATE_LOCK around programming surface flip. - Remove the now unused graphic surface lock. - Add macros to get and set four registers - both immediate and H Retrace should not be enabled at the same time
Signed-off-by: Andrew Wong <andrew.wong1@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
Revision tags: v4.9, v4.9-rc8 |
|
#
22f050be |
| 30-Nov-2016 |
Roman Li <Roman.Li@amd.com> |
drm/amd/display: fix REG_SET_5 macro
Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <Harry.
drm/amd/display: fix REG_SET_5 macro
Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|
#
4562236b |
| 12-Sep-2017 |
Harry Wentland <harry.wentland@amd.com> |
drm/amd/dc: Add dc display driver (v2)
Supported DCE versions: 8.0, 10.0, 11.0, 11.2
v2: rebase against 4.11
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexande
drm/amd/dc: Add dc display driver (v2)
Supported DCE versions: 8.0, 10.0, 11.0, 11.2
v2: rebase against 4.11
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
|