#
5f36d1ce |
| 10-Apr-2024 |
Francois Dugast <francois.dugast@intel.com> |
drm/xe/gt: Add L3 bank mask to GT topology
Generate the mask of enabled L3 banks for the GT. It is stored with the rest of the GT topology in a consistent representation across platforms. For now th
drm/xe/gt: Add L3 bank mask to GT topology
Generate the mask of enabled L3 banks for the GT. It is stored with the rest of the GT topology in a consistent representation across platforms. For now the L3 bank mask is just printed in the log for developers to easily figure out the fusing characteristics of machines that they are trying to debug issues on. Later it can be used to replace existing code in the driver that requires the L3 bank count (not mask). Also the mask can easily be exposed to user space in a new query if needed.
v2: Better naming of variable and function (Matt Roper)
Bspec: 52545, 52546, 62482 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Francois Dugast <francois.dugast@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240410123723.7-2-francois.dugast@intel.com
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#
7cd05ef8 |
| 08-Apr-2024 |
Gustavo Sousa <gustavo.sousa@intel.com> |
drm/xe/xe2hpm: Add initial set of workarounds
Define the initial set of workarounds for Xe2_HPM.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Balasubramani Vivekanandan <ba
drm/xe/xe2hpm: Add initial set of workarounds
Define the initial set of workarounds for Xe2_HPM.
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-12-balasubramani.vivekanandan@intel.com
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#
7f3ee7d8 |
| 08-Apr-2024 |
Haridhar Kalvala <haridhar.kalvala@intel.com> |
drm/xe/xe2hpg: Add initial GT workarounds
Add the initial set of Xe2_HPG gt/engine/lrc workarounds.
v2: Removed WA_16020183090 which is no more applicable Extended WA_18033852989,18034896535 al
drm/xe/xe2hpg: Add initial GT workarounds
Add the initial set of Xe2_HPG gt/engine/lrc workarounds.
v2: Removed WA_16020183090 which is no more applicable Extended WA_18033852989,18034896535 also to xe2hpg
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Signed-off-by: Dnyaneshar Bhadane <dnyaneshwar.bhadane@intel.com> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-10-balasubramani.vivekanandan@intel.com
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#
b5c2ca03 |
| 08-Apr-2024 |
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> |
drm/xe/xe2hpg: Determine flat ccs offset for vram
on Xe2 dgfx platform determine the offset using Flat CCS size bitfield of XE2_FLAT_CCS_BASE_RANGE_[UPPER/LOWER] mcr registers.
v2: function argumen
drm/xe/xe2hpg: Determine flat ccs offset for vram
on Xe2 dgfx platform determine the offset using Flat CCS size bitfield of XE2_FLAT_CCS_BASE_RANGE_[UPPER/LOWER] mcr registers.
v2: function argument tile_size changed from pass by reference to pass by value
Bspec: 68023 Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240408170545.3769566-7-balasubramani.vivekanandan@intel.com
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#
9f18b55b |
| 01-Apr-2024 |
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> |
drm/xe/xe2: Add workaround 18033852989
This workaround applies to RCS engine's context, hence added as LRC workaround.
v2 - Fix commit description as lrc workaround instead of engine.(Lucas)
v3 -
drm/xe/xe2: Add workaround 18033852989
This workaround applies to RCS engine's context, hence added as LRC workaround.
v2 - Fix commit description as lrc workaround instead of engine.(Lucas)
v3 - COMMON_SLICE_CHICKEN1 is a masked register, add XE_REG_OPTION_MASKED flag. (Matt)
BSPEC: 55899
Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240401163806.3821128-1-himal.prasad.ghimiray@intel.com
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#
d62753a5 |
| 26-Mar-2024 |
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> |
drm/xe/gsc: Implement WA 14018094691
The WA states that we need to keep the primary GT powered up during GSC load to allow the GSC FW to access its registers. We also need to make sure that one of t
drm/xe/gsc: Implement WA 14018094691
The WA states that we need to keep the primary GT powered up during GSC load to allow the GSC FW to access its registers. We also need to make sure that one of the registers is locked before starting the load.
v2: fix location of register def (Matt)
Bspec: 55928 Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240326224456.518548-1-daniele.ceraolospurio@intel.com
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#
0267ee19 |
| 18-Mar-2024 |
Radhakrishna Sripada <radhakrishna.sripada@intel.com> |
drm/xe/xelpg: Add Wa_14020495402
Disable clockgating for TDL SVHS fub.
v2: Extend the Wa to 1274(MattR)
Bspec: 46045 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna
drm/xe/xelpg: Add Wa_14020495402
Disable clockgating for TDL SVHS fub.
v2: Extend the Wa to 1274(MattR)
Bspec: 46045 Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240318210120.564692-1-radhakrishna.sripada@intel.com
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#
42b266be |
| 14-Mar-2024 |
Michal Wajdeczko <michal.wajdeczko@intel.com> |
drm/xe: Mark VF accessible interrupt registers
Interrupt registers 1900xx are VF accessible but only until version 12.50 as on newer platforms VFs are using memory-based interrupts.
To avoid comple
drm/xe: Mark VF accessible interrupt registers
Interrupt registers 1900xx are VF accessible but only until version 12.50 as on newer platforms VFs are using memory-based interrupts.
To avoid complexity, we mark those registers with XE_REG_OPTION_VF unconditionally, as IRQ handling on newer VFs is different anyway.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240314173130.1177-6-michal.wajdeczko@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
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#
cc244ce5 |
| 04-Mar-2024 |
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> |
drm/xe/gsc: Handle GSCCS ER interrupt
Starting on Xe2, the GSCCS engine reset is a 2-step process. When the driver or the GuC hits the GDRST register, the CS is immediately reset and a success is re
drm/xe/gsc: Handle GSCCS ER interrupt
Starting on Xe2, the GSCCS engine reset is a 2-step process. When the driver or the GuC hits the GDRST register, the CS is immediately reset and a success is reported, but the GSC shim continues its reset in the background. While the shim reset is ongoing, the CS is able to accept new context submission, but any commands that require the shim will be stalled until the reset is completed. This means that we can keep submitting to the GSCCS as long as we make sure that the preemption timeout is big enough to cover any delay introduced by the reset; since the GSC preempt timeout is not tunable at runtime, we only need to check that the value set in kconfig is big enough (and increase it if it isn't). When the shim reset completes, a specific CS interrupt is triggered, in response to which we need to check the GSCI_TIMER_STATUS register to see if the reset was successful or not. Note that the GSCI_TIMER_STATUS register is not power save/restored, so it gets reset on MC6 entry. However, a reset failure stops MC6, so in that scenario we're always guaranteed to find the correct value.
Since we can't check the register within interrupt context, the existing GSC worker has been updated to handle it. The expected action to take on ER failure is to trigger a driver FLR, but we still don't support that, so for now we just print an error. A comment has been added to the code to keep track of the FLR requirement.
v2: Add a check for the initial timeout value (Alan)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240304145634.820684-1-daniele.ceraolospurio@intel.com
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#
404669db |
| 01-Feb-2024 |
Karthik Poosa <karthik.poosa@intel.com> |
drm/xe/hwmon: Refactor xe hwmon
Check latest platform first in xe_hwmon_get_reg. Move PVC HWMON registers to regs/xe_pcode.h.
Suggested-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Kar
drm/xe/hwmon: Refactor xe hwmon
Check latest platform first in xe_hwmon_get_reg. Move PVC HWMON registers to regs/xe_pcode.h.
Suggested-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Karthik Poosa <karthik.poosa@intel.com> Reviewed-by: Badal Nilawar <badal.nilawar@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240201180600.434822-1-karthik.poosa@intel.com
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#
02c4e64a |
| 23-Jan-2024 |
Shekhar Chauhan <shekhar.chauhan@intel.com> |
drm/xe/xe2_lpg: Introduce performance guide changes
Add performance guide changes to Xe2_LPG.
BSpec: 72161 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthe
drm/xe/xe2_lpg: Introduce performance guide changes
Add performance guide changes to Xe2_LPG.
BSpec: 72161 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240123050552.2250699-2-shekhar.chauhan@intel.com
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#
eb08104f |
| 17-Jan-2024 |
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> |
drm/xe/gsc: add support for GSC proxy interrupt
The GSC notifies us of a proxy request via the HECI2 interrupt. The interrupt must be enabled both in the HECI layer and in our usual gt irq programmi
drm/xe/gsc: add support for GSC proxy interrupt
The GSC notifies us of a proxy request via the HECI2 interrupt. The interrupt must be enabled both in the HECI layer and in our usual gt irq programming; for the latter, the interrupt is enabled via the same enable register as the GSC CS, but it does have its own mask register. When the interrupt is received, we also need to de-assert it in both layers.
The handling of the proxy request is deferred to the same worker that we use for GSC load. New flags have been added to distinguish between the init case and the proxy interrupt.
v2: rename irq define, fix include ordering (Alan)
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240117182621.2653049-3-daniele.ceraolospurio@intel.com
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#
9fbedddf |
| 09-Jan-2024 |
Shekhar Chauhan <shekhar.chauhan@intel.com> |
drm/xe/xe2_lpg: Add Wa_16018610683
Force max 128KB SLM during WMTP PASS1 Restore.
BSpec: 70202 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@in
drm/xe/xe2_lpg: Add Wa_16018610683
Force max 128KB SLM during WMTP PASS1 Restore.
BSpec: 70202 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20240109055550.679289-1-shekhar.chauhan@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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#
ddb5bade |
| 04-Jan-2024 |
Nirmoy Das <nirmoy.das@intel.com> |
drm/xe/xe2: synchronise CS_CHICKEN1 with WMTP support
Recommendation is to read FUSE4 register to check if WMTP has been enabled/disabled by HW. If enabled we don't need to do anything special, howe
drm/xe/xe2: synchronise CS_CHICKEN1 with WMTP support
Recommendation is to read FUSE4 register to check if WMTP has been enabled/disabled by HW. If enabled we don't need to do anything special, however if disabled recommendation is to also disable the WMTP mode in the FF_SLICE_CS_CHICKEN2 register, falling back to thread-group and mid-batch preemption only. However on Linux, the per-context CS_CHICKEN1 is how userspace controls pre-emption, so instead use the default lrc to disable WMTP using CS_CHICKEN1, if disabled by HW. Userspace is still free to set CS_CHICKEN1 to whatever they want later.
v2: remove redundant version check and also add descriptive name(Matt) v3: remove usage of REG_FIELD_GET(Matt)
Cc: Matt Roper <matthew.d.roper@intel.com> Co-developed-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20240104182615.21327-1-nirmoy.das@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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#
7158a688 |
| 18-Dec-2023 |
Michal Wajdeczko <michal.wajdeczko@intel.com> |
drm/xe: Update definition of GT_INTR_DW
Add bits definitions that we will be using in upcoming patch.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20231214185
drm/xe: Update definition of GT_INTR_DW
Add bits definitions that we will be using in upcoming patch.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://lore.kernel.org/r/20231214185955.1791-5-michal.wajdeczko@intel.com Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
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#
90a8b23f |
| 15-Dec-2023 |
Ashutosh Dixit <ashutosh.dixit@intel.com> |
drm/xe/pmu: Remove PMU from Xe till uapi is finalized
PMU uapi is likely to change in the future. Till the uapi is finalized, remove PMU from Xe. PMU can be re-added after uapi is finalized.
v2: In
drm/xe/pmu: Remove PMU from Xe till uapi is finalized
PMU uapi is likely to change in the future. Till the uapi is finalized, remove PMU from Xe. PMU can be re-added after uapi is finalized.
v2: Include xe_drm.h in xe/tests/xe_dma_buf.c (Francois)
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com> Acked-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com> Acked-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Acked-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Mateusz Naklicki <mateusz.naklicki@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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#
aaa536a8 |
| 14-Dec-2023 |
Matt Roper <matthew.d.roper@intel.com> |
drm/xe: Re-sort GT register header
Keeping the register definitions sorted will make it easy to find existing definitions and prevent accidental introduction of duplicate definitions.
v2: - Reorde
drm/xe: Re-sort GT register header
Keeping the register definitions sorted will make it easy to find existing definitions and prevent accidental introduction of duplicate definitions.
v2: - Reorder FUSE3/FUSE4 registers and move GT0_PERF_LIMIT_REASONS / MTL_MEDIA_PERF_LIMIT_REASONS to proper places. (Lucas)
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20231214184659.2249559-17-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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#
93536c2b |
| 14-Dec-2023 |
Matt Roper <matthew.d.roper@intel.com> |
drm/xe: Define interrupt vector bits with the interrupt registers
The bit definitions had become a bit orphaned; move them to the same location as the interrupt registers that they're used with.
Re
drm/xe: Define interrupt vector bits with the interrupt registers
The bit definitions had become a bit orphaned; move them to the same location as the interrupt registers that they're used with.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20231214184659.2249559-16-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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#
5ea7fe65 |
| 14-Dec-2023 |
Matt Roper <matthew.d.roper@intel.com> |
drm/xe: Move some per-engine register definitions to the engine header
Although we only work with the RCS instances today, the FF_SLICE_CS_CHICKEN1[1,2] CS_DEBUG_MODE1, CS_CHICKEN1, and FF_THREAD_MO
drm/xe: Move some per-engine register definitions to the engine header
Although we only work with the RCS instances today, the FF_SLICE_CS_CHICKEN1[1,2] CS_DEBUG_MODE1, CS_CHICKEN1, and FF_THREAD_MODE registers all have instances on both the RCS and CCS engines. Convert these to parameterized macros and move them to the engine register header.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/20231214184659.2249559-12-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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#
4cb12b71 |
| 12-Dec-2023 |
Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> |
drm/xe/xe2: Determine bios enablement for flat ccs on igfx
If bios disables flat ccs on igfx make has_flat_ccs as 0 and notify via drm_dbg.
Bspec:59255
v2: - Release forcewake. - Add registers i
drm/xe/xe2: Determine bios enablement for flat ccs on igfx
If bios disables flat ccs on igfx make has_flat_ccs as 0 and notify via drm_dbg.
Bspec:59255
v2: - Release forcewake. - Add registers in order. - drop dgfx condition and only add it back in the future when the support for an Xe2 dgpu will be added. - Use drm_dbg instead of drm_info. (Matt)
v3: - Address nit(Matt)
Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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#
1c8e9019 |
| 08-Dec-2023 |
Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> |
drm/xe: Add frequency throttle reasons sysfs attributes
Add throttle reasons sysfs attributes under a separate directory.
/device/tile<n>/gt<n>/freq0/throttle |- reason_pl1 |- reason_pl2 |
drm/xe: Add frequency throttle reasons sysfs attributes
Add throttle reasons sysfs attributes under a separate directory.
/device/tile<n>/gt<n>/freq0/throttle |- reason_pl1 |- reason_pl2 |- reason_pl4 |- reason_prochot |- reason_ratl |- reason_vr_tdc |- reason_vr_thermalert |- status
v2: Remove unnecessary headers and clean-up action (Riana)
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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#
0d97ecce |
| 09-Oct-2023 |
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> |
drm/xe: Enable Fixed CCS mode setting
Disable dynamic HW load balancing of compute resource assignment to engines and instead enabled fixed mode of mapping compute resources to engines on all platfo
drm/xe: Enable Fixed CCS mode setting
Disable dynamic HW load balancing of compute resource assignment to engines and instead enabled fixed mode of mapping compute resources to engines on all platforms with more than one compute engine.
By default enable only one CCS engine with all compute slices assigned to it. This is the desired configuration for common workloads.
PVC platform supports only the fixed CCS mode (workaround 16016805146).
v2: Rebase, make it platform agnostic v3: Minor code refactoring
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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#
6a1fd678 |
| 05-Dec-2023 |
Tejas Upadhyay <tejas.upadhyay@intel.com> |
drm/xe/xe2: Add workaround 14019988906
This workaround applies to Graphics 20.04 as engine workaround
V2(MattR): - Reorder bit define - Apply WA for RCS only
Reviewed-by: Matt Roper <matthew.d.r
drm/xe/xe2: Add workaround 14019988906
This workaround applies to Graphics 20.04 as engine workaround
V2(MattR): - Reorder bit define - Apply WA for RCS only
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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#
975e4a37 |
| 18-Nov-2023 |
Vinay Belgaumkar <vinay.belgaumkar@intel.com> |
drm/xe: Manually setup C6 when skip_guc_pc is set
Skip the init/start/stop GuC PC functions and toggle C6 using register writes instead. Also request max possible frequency as dynamic freq managemen
drm/xe: Manually setup C6 when skip_guc_pc is set
Skip the init/start/stop GuC PC functions and toggle C6 using register writes instead. Also request max possible frequency as dynamic freq management is disabled.
v2: Fix compile warning
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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a409901f |
| 20-Nov-2023 |
Tejas Upadhyay <tejas.upadhyay@intel.com> |
drm/xe/xe2: Add workaround 14020013138
This workaround applies to Xe2_LPG A0
V3: - Apply rule RENDER class V2(Matt): - Apply WA in lrc context
Reviewed-by: Matt Roper <matthew.d.roper@intel.co
drm/xe/xe2: Add workaround 14020013138
This workaround applies to Xe2_LPG A0
V3: - Apply rule RENDER class V2(Matt): - Apply WA in lrc context
Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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