#
2bcf0f9b |
| 26-Mar-2024 |
Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> |
drm/i915: Add new PCI IDs to DG2 platform in driver
New PCI IDs are added in Bspec for DG2 platform, add them in driver
Bspec: 44477 Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.
drm/i915: Add new PCI IDs to DG2 platform in driver
New PCI IDs are added in Bspec for DG2 platform, add them in driver
Bspec: 44477 Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240326103241.3832494-1-ravi.kumar.vodapalli@intel.com
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#
425b4638 |
| 14-Feb-2024 |
Gustavo Sousa <gustavo.sousa@intel.com> |
drm/i915: Update ADL-N PCI IDs
Extend the list of ADL-N PCI IDs to contain two new entries.
Bspec: 68397 Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Dnyaneshwar Bhadane <dny
drm/i915: Update ADL-N PCI IDs
Extend the list of ADL-N PCI IDs to contain two new entries.
Bspec: 68397 Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240214144629.106702-2-gustavo.sousa@intel.com
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#
bddacdf4 |
| 08-Jan-2024 |
Matt Roper <matthew.d.roper@intel.com> |
drm/i915: Add additional ARL PCI IDs
Our existing MTL driver handling is also sufficient to handle ARL, so these IDs are simply added to the MTL ID list.
Bspec: 55420 Signed-off-by: Matt Roper <mat
drm/i915: Add additional ARL PCI IDs
Our existing MTL driver handling is also sufficient to handle ARL, so these IDs are simply added to the MTL ID list.
Bspec: 55420 Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240108122738.14399-2-haridhar.kalvala@intel.com
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#
5032c607 |
| 20-Nov-2023 |
Haridhar Kalvala <haridhar.kalvala@intel.com> |
drm/i915: ATS-M device ID update
ATS-M device ID update.
BSpec: 44477
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by
drm/i915: ATS-M device ID update
ATS-M device ID update.
BSpec: 44477
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231120113731.1570589-1-haridhar.kalvala@intel.com
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#
d0c908d2 |
| 11-Oct-2023 |
Shekhar Chauhan <shekhar.chauhan@intel.com> |
drm/i915: Add new DG2 PCI IDs
Add recently added PCI IDs for DG2
BSpec: 44477 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-o
drm/i915: Add new DG2 PCI IDs
Add recently added PCI IDs for DG2
BSpec: 44477 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231011080039.2781048-1-shekhar.chauhan@intel.com
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#
5d5fea7c |
| 24-Aug-2023 |
Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> |
drm/i915/rpl: Update pci ids for RPL P/U
Update pci device ids as per bspec for RPL P/U.
v2: - Append new id's instead of replacing the existing in device id list define
v3: - Fixed the commit mes
drm/i915/rpl: Update pci ids for RPL P/U
Update pci device ids as per bspec for RPL P/U.
v2: - Append new id's instead of replacing the existing in device id list define
v3: - Fixed the commit messege with revision details.
Bpsec: 55376 Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230824062840.2372872-1-dnyaneshwar.bhadane@intel.com
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#
8940da9f |
| 22-Aug-2023 |
Nemesa Garg <nemesa.garg@intel.com> |
drm/i915/mtl: Adding DeviceID for Arrowlake-S under MTL
Arrowlake-S graphics is similar enough to Meteorlake that we can treat them as the same platform
Signed-off-by: Nemesa Garg <nemesa.garg@inte
drm/i915/mtl: Adding DeviceID for Arrowlake-S under MTL
Arrowlake-S graphics is similar enough to Meteorlake that we can treat them as the same platform
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230822172743.2113377-1-nemesa.garg@intel.com
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#
2e3c369f |
| 21-Aug-2023 |
Matt Roper <matthew.d.roper@intel.com> |
drm/i915/mtl: Eliminate subplatforms
Now that we properly match the Xe_LPG IP versions associated with various workarounds, there's no longer any need to define separate MTL subplatform in the drive
drm/i915/mtl: Eliminate subplatforms
Now that we properly match the Xe_LPG IP versions associated with various workarounds, there's no longer any need to define separate MTL subplatform in the driver. Nothing in the code is conditional on MTL-M or MTL-P base platforms. Furthermore, I'm not sure the "M" and "P" designations are even an accurate representation of which specific platforms would have which IP versions; those were mostly just placeholders from a long time ago. The reality is that the IP version present on a platform gets read from a fuse register at driver init; we shouldn't be trying to guess which IP is present based on PCI ID anymore.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-18-matthew.d.roper@intel.com
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#
61b795a9 |
| 30-Jan-2023 |
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> |
drm/i915: Add RPL-U sub platform
Separate out RPLU device ids and add them to both RPL and newly created RPL-U subplatforms.
v2: (Matt) - Sort PCI-IDs numerically - Name the sub-platform to
drm/i915: Add RPL-U sub platform
Separate out RPLU device ids and add them to both RPL and newly created RPL-U subplatforms.
v2: (Matt) - Sort PCI-IDs numerically - Name the sub-platform to accurately depict what it is for - Make RPL-U part of RPL subplatform
v3: revert to RPL-U subplatform (Jani)
v4: (Jani) - Add RPL-U ids to RPL-P platform - Remove redundant comment
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-2-chaitanya.kumar.borah@intel.com
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#
3a38be31 |
| 08-Feb-2023 |
Matt Roper <matthew.d.roper@intel.com> |
drm/i915/dg2: Drop one PCI ID
The bspec was recently updated to remove PCI ID 0x5698; this ID is actually reserved for future use and should not be treated as DG2-G11.
Bspec: 44477 Fixes: 8618b8489
drm/i915/dg2: Drop one PCI ID
The bspec was recently updated to remove PCI ID 0x5698; this ID is actually reserved for future use and should not be treated as DG2-G11.
Bspec: 44477 Fixes: 8618b8489ba6 ("drm/i915: DG2 and ATS-M device ID updates") Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230208200905.680865-1-matthew.d.roper@intel.com
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#
54762e92 |
| 06-Feb-2023 |
Jonathan Gray <jsg@jsg.id.au> |
drm/i915: Add another EHL pci id
described as "32 Execution Unit (EU) Super SKU" in: Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series Processors for IoT Applications Datasheet,
drm/i915: Add another EHL pci id
described as "32 Execution Unit (EU) Super SKU" in: Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series Processors for IoT Applications Datasheet, Volume 1 Document Number: 636112-1.6
Signed-off-by: Jonathan Gray <jsg@jsg.id.au> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230206043727.46069-1-jsg@jsg.id.au
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#
6215a7c8 |
| 24-Aug-2022 |
José Roberto de Souza <jose.souza@intel.com> |
drm/i915: Add new ADL-S pci id
New PCI id recently added.
BSpec: 53655 Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakana
drm/i915: Add new ADL-S pci id
New PCI id recently added.
BSpec: 53655 Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220824133935.51560-1-jose.souza@intel.com
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#
78353039 |
| 08-Jul-2022 |
Radhakrishna Sripada <radhakrishna.sripada@intel.com> |
drm/i915/mtl: Add MeteorLake PCI IDs
Add Meteorlake PCI IDs. Split into M, and P subplatforms.
v2: Update PCI id's v3: Move id 7d60 under MTL_M(MattR)
Bspec: 55420
Signed-off-by: Radhakrishna Sri
drm/i915/mtl: Add MeteorLake PCI IDs
Add Meteorlake PCI IDs. Split into M, and P subplatforms.
v2: Update PCI id's v3: Move id 7d60 under MTL_M(MattR)
Bspec: 55420
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220708000335.2869311-3-radhakrishna.sripada@intel.com
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#
8618b848 |
| 01-Jul-2022 |
Matt Roper <matthew.d.roper@intel.com> |
drm/i915: DG2 and ATS-M device ID updates
Small BAR support has now landed, which allows us to add the PCI IDs that correspond to add-in card designs of DG2 and ATS-M. There's also one additional M
drm/i915: DG2 and ATS-M device ID updates
Small BAR support has now landed, which allows us to add the PCI IDs that correspond to add-in card designs of DG2 and ATS-M. There's also one additional MB-down PCI ID that recently appeared (0x5698) so we add it too.
Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220701152231.529511-2-matthew.d.roper@intel.com
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#
1bc4ae0c |
| 25-Apr-2022 |
Matt Roper <matthew.d.roper@intel.com> |
drm/i915: Add first set of DG2 PCI IDs
The IDs added here are the subset reserved for 'motherboard down' designs of DG2. We have all the necessary support upstream to enable these now (although the
drm/i915: Add first set of DG2 PCI IDs
The IDs added here are the subset reserved for 'motherboard down' designs of DG2. We have all the necessary support upstream to enable these now (although they'll continue to require force_probe until the usual requirements are met).
The remaining DG2 IDs for add-in cards will come in a future patch once some additional required functionality has fully landed.
Bspec: 44477 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Dave Airlie <airlied@gmail.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220425211251.77154-3-matthew.d.roper@intel.com
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#
72c3c8d6 |
| 18-Apr-2022 |
Matt Atwood <matthew.s.atwood@intel.com> |
drm/i915/rpl-p: Add PCI IDs
Adding initial PCI ids for RPL-P. RPL-P behaves identically to ADL-P from i915's point of view.
Changes since V1 : - SUBPLATFORM ADL_N and RPL_P clash as both are ADLP
drm/i915/rpl-p: Add PCI IDs
Adding initial PCI ids for RPL-P. RPL-P behaves identically to ADL-P from i915's point of view.
Changes since V1 : - SUBPLATFORM ADL_N and RPL_P clash as both are ADLP based - Matthew R
Bspec: 55376 Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> [mattrope: Corrected comment formatting to match coding style] Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220418062157.2974665-1-tejaskumarx.surendrakumar.upadhyay@intel.com
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#
756b807f |
| 22-Mar-2022 |
Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> |
drm/i915: Add RPL-S PCI IDs
Add couple of RPL-S device ids
Bspec : 53655 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Revi
drm/i915: Add RPL-S PCI IDs
Add couple of RPL-S device ids
Bspec : 53655 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220322040616.1078009-1-tejaskumarx.surendrakumar.upadhyay@intel.com
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#
7e28d0b2 |
| 10-Dec-2021 |
Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> |
drm/i915/adl-n: Enable ADL-N platform
Adding PCI device ids and enabling ADL-N platform. ADL-N from i915 point of view is subplatform of ADL-P.
BSpec: 68397
Changes since V2: - Added version log
drm/i915/adl-n: Enable ADL-N platform
Adding PCI device ids and enabling ADL-N platform. ADL-N from i915 point of view is subplatform of ADL-P.
BSpec: 68397
Changes since V2: - Added version log history Changes since V1: - replace IS_ALDERLAKE_N with IS_ADLP_N - Jani Nikula
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211210051802.4063958-1-tejaskumarx.surendrakumar.upadhyay@intel.com
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#
52407c22 |
| 03-Dec-2021 |
Anusha Srivatsa <anusha.srivatsa@intel.com> |
drm/i915/rpl-s: Add PCI IDS for Raptor Lake S
Raptor Lake S(RPL-S) is a version 12 Display, Media and Render. For all i915 purposes it is the same as Alder Lake S (ADL-S).
Introduce RPL-S as a subp
drm/i915/rpl-s: Add PCI IDS for Raptor Lake S
Raptor Lake S(RPL-S) is a version 12 Display, Media and Render. For all i915 purposes it is the same as Alder Lake S (ADL-S).
Introduce RPL-S as a subplatform of ADL-S. This patch adds PCI ids for RPL-S.
BSpec: 53655 Cc: x86@kernel.org Cc: dri-devel@lists.freedesktop.org Cc: Ingo Molnar <mingo@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Dave Hansen <dave.hansen@linux.intel.com> # arch/x86 Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211203063545.2254380-2-anusha.srivatsa@intel.com
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#
5f0d4214 |
| 13-Sep-2021 |
José Roberto de Souza <jose.souza@intel.com> |
drm/i915/dg1: Add new PCI id
New DG1 PCI id.
BSpec: 44463 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel
drm/i915/dg1: Add new PCI id
New DG1 PCI id.
BSpec: 44463 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210913181909.35237-1-jose.souza@intel.com
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#
c79b846f |
| 18-Aug-2021 |
Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> |
drm/i915/adl_s: Update ADL-S PCI IDs
Sync PCI IDs with Bspec.
Bspec:53655
Changes since V2: - Upstream devices which are "POR" yes and "Ok to upstream" yes - James Asmus Changes since V1:
drm/i915/adl_s: Update ADL-S PCI IDs
Sync PCI IDs with Bspec.
Bspec:53655
Changes since V2: - Upstream devices which are "POR" yes and "Ok to upstream" yes - James Asmus Changes since V1: - All POR and Non POR Ids needs to be upstreamed - James Asmus
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210818050116.1116237-1-tejaskumarx.surendrakumar.upadhyay@intel.com
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#
760759f2 |
| 06-May-2021 |
Clinton Taylor <Clinton.A.Taylor@intel.com> |
drm/i915/adl_p: Add PCI Devices IDs
Add 18 known PCI device IDs
Bspec: 55376 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@i
drm/i915/adl_p: Add PCI Devices IDs
Add 18 known PCI device IDs
Bspec: 55376 Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-3-imre.deak@intel.com
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#
3f50033d |
| 03-Feb-2021 |
Anand Moon <anandx.ram.moon@intel.com> |
drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGA
As per Bspec: 53655 Update PCI ids for Mobile BGA.
Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@li
drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGA
As per Bspec: 53655 Update PCI ids for Mobile BGA.
Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Anand Moon <anandx.ram.moon@intel.com> Reviewed-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210203091029.2089-1-anandx.ram.moon@intel.com
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#
0883d63b |
| 19-Jan-2021 |
Caz Yokoyama <caz.yokoyama@intel.com> |
drm/i915/adl_s: Add ADL-S platform info and PCI ids
- Add the initial platform information for Alderlake-S. - Specify ppgtt_size value - Add dma_mask_size - Add ADLS REVIDs - HW tracking(Selective U
drm/i915/adl_s: Add ADL-S platform info and PCI ids
- Add the initial platform information for Alderlake-S. - Specify ppgtt_size value - Add dma_mask_size - Add ADLS REVIDs - HW tracking(Selective Update Tracking Enable) has been removed from ADLS. Disable PSR2 till we enable software/ manual tracking.
v2: - Add support for different ADLS SOC steppings to select correct GT/DISP stepping based on Bspec 53655 based on feedback from Matt Roper.(aswarup)
v3: - Make display/gt steppings info generic for reuse with TGL and ADLS. - Modify the macros to reuse tgl_revids_get() - Add HTI support to adls device info.(mdroper)
v4: - Rebase on TGL patch for applying WAs based on stepping info from Matt Roper's feedback.(aswarup)
v5: - Replace macros with PCI IDs in revid to stepping table.
v6: remove stray adls_revids (Lucas)
Bspec: 53597 Bspec: 53648 Bspec: 53655 Bspec: 48028 Bspec: 53650 BSpec: 50422
Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210119192931.1116500-2-lucas.demarchi@intel.com
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04057a1a |
| 30-Oct-2020 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
drm/i915: Sort EHL/JSL PCI IDs
Sort the EHL/JSL PCI IDs numerically. Some order seems better than randomness.
v2: Deal with the JSL vs. EHL split v3: Rebase due to 0x4500 removal
Reviewed-by: Anus
drm/i915: Sort EHL/JSL PCI IDs
Sort the EHL/JSL PCI IDs numerically. Some order seems better than randomness.
v2: Deal with the JSL vs. EHL split v3: Rebase due to 0x4500 removal
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> #v1 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201030164124.16922-1-ville.syrjala@linux.intel.com
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