Revision tags: v5.18-rc5, v5.18-rc4, v5.18-rc3, v5.18-rc2, v5.18-rc1, v5.17, v5.17-rc8, v5.17-rc7, v5.17-rc6, v5.17-rc5, v5.17-rc4, v5.17-rc3, v5.17-rc2, v5.17-rc1, v5.16, v5.16-rc8, v5.16-rc7, v5.16-rc6, v5.16-rc5, v5.16-rc4, v5.16-rc3, v5.16-rc2, v5.16-rc1, v5.15, v5.15-rc7, v5.15-rc6, v5.15-rc5, v5.15-rc4, v5.15-rc3, v5.15-rc2, v5.15-rc1, v5.14, v5.14-rc7, v5.14-rc6, v5.14-rc5, v5.14-rc4, v5.14-rc3, v5.14-rc2, v5.14-rc1, v5.13, v5.13-rc7, v5.13-rc6, v5.13-rc5, v5.13-rc4 |
|
#
c586f53a |
| 28-May-2021 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx8mq: remove SYS PLL 1/2 clock gates
Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks the uSDHC module which is sporadically unable to enumerate devices after this
clk: imx8mq: remove SYS PLL 1/2 clock gates
Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks the uSDHC module which is sporadically unable to enumerate devices after this change. Also it makes AMP clock management harder with no obvious benefit to Linux, so just revert the change.
Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de Fixes: b04383b6a558 ("clk: imx8mq: Define gates for pll1/2 fixed dividers") Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
show more ...
|
Revision tags: v5.13-rc3, v5.13-rc2, v5.13-rc1, v5.12, v5.12-rc8, v5.12-rc7, v5.12-rc6, v5.12-rc5, v5.12-rc4, v5.12-rc3, v5.12-rc2, v5.12-rc1-dontuse, v5.11, v5.11-rc7, v5.11-rc6 |
|
#
75a352bc |
| 25-Jan-2021 |
Lucas Stach <l.stach@pengutronix.de> |
clk: imx8mq: add PLL monitor output
The PLL monitor is mentioned as a debug feature in the reference manual, but there are some boards that use this clock output as a reference clock for board level
clk: imx8mq: add PLL monitor output
The PLL monitor is mentioned as a debug feature in the reference manual, but there are some boards that use this clock output as a reference clock for board level components. Add support for those clocks in the clock driver, so this clock output can be used properly.
Note that the VIDEO1, GPU and VPU mux inputs are rotated compared to the description in the reference manual. The order in this patch has been empirically validated.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
Revision tags: v5.11-rc5, v5.11-rc4, v5.11-rc3, v5.11-rc2, v5.11-rc1, v5.10, v5.10-rc7, v5.10-rc6, v5.10-rc5, v5.10-rc4, v5.10-rc3, v5.10-rc2, v5.10-rc1, v5.9, v5.9-rc8, v5.9-rc7, v5.9-rc6, v5.9-rc5, v5.9-rc4, v5.9-rc3, v5.9-rc2, v5.9-rc1, v5.8, v5.8-rc7, v5.8-rc6, v5.8-rc5, v5.8-rc4, v5.8-rc3, v5.8-rc2, v5.8-rc1, v5.7, v5.7-rc7, v5.7-rc6, v5.7-rc5, v5.7-rc4, v5.7-rc3, v5.7-rc2, v5.7-rc1, v5.6, v5.6-rc7, v5.6-rc6, v5.6-rc5, v5.6-rc4, v5.6-rc3 |
|
#
d6fb02f0 |
| 19-Feb-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: imx8mq: fix a53 cpu clock
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz whi
clk: imx: imx8mq: fix a53 cpu clock
The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which violates the CCM.
There is a CORE_SEL slice before A53 core, we need to configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out. Configure a53 ccm root sources from 800MHz sys pll Configure a53 core sources from arm_pll_out Mark arm_a53_core as critical clock
Fixes: db27e40b27f1 ("clk: imx8mq: Add the missing ARM clock") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
Revision tags: v5.6-rc2, v5.6-rc1 |
|
#
7a8d3b90 |
| 28-Jan-2020 |
Peng Fan <peng.fan@nxp.com> |
clk: imx: imx8mq: use imx8m_clk_hw_composite_core
Use imx8m_clk_hw_composite_core to simplify code.
Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatib
clk: imx: imx8mq: use imx8m_clk_hw_composite_core
Use imx8m_clk_hw_composite_core to simplify code.
Add new definitions, and X_SRC/CG/DIV will be alias to the new definitions for backwards compatibility
Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
Revision tags: v5.5, v5.5-rc7, v5.5-rc6, v5.5-rc5, v5.5-rc4, v5.5-rc3, v5.5-rc2, v5.5-rc1, v5.4, v5.4-rc8, v5.4-rc7, v5.4-rc6, v5.4-rc5, v5.4-rc4 |
|
#
b04383b6 |
| 16-Oct-2019 |
Leonard Crestez <leonard.crestez@nxp.com> |
clk: imx8mq: Define gates for pll1/2 fixed dividers
On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate but these gates are not currently defined in the cl
clk: imx8mq: Define gates for pll1/2 fixed dividers
On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2 each with their own gate but these gates are not currently defined in the clock tree.
Add them between sys1/2_pll_out and the fixed dividers.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
Revision tags: v5.4-rc3, v5.4-rc2 |
|
#
f0b1d7f2 |
| 02-Oct-2019 |
Laurentiu Palcu <laurentiu.palcu@nxp.com> |
clk: imx8mq: Add VIDEO2_PLL clock
This clock is needed by DCSS when high resolutions are used.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com> CC: Abel Vesa <abel.vesa@nxp.com> Signed-off-
clk: imx8mq: Add VIDEO2_PLL clock
This clock is needed by DCSS when high resolutions are used.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com> CC: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
Revision tags: v5.4-rc1, v5.3, v5.3-rc8, v5.3-rc7, v5.3-rc6, v5.3-rc5, v5.3-rc4, v5.3-rc3, v5.3-rc2, v5.3-rc1, v5.2, v5.2-rc7, v5.2-rc6, v5.2-rc5, v5.2-rc4, v5.2-rc3, v5.2-rc2 |
|
#
87def8d0 |
| 22-May-2019 |
Leonard Crestez <leonard.crestez@nxp.com> |
dt-bindings: clock: imx8m: Add GIC clock
This should be defined in the clock tree so that parents are not shutdown by accident
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by:
dt-bindings: clock: imx8m: Add GIC clock
This should be defined in the clock tree so that parents are not shutdown by accident
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
Revision tags: v5.2-rc1 |
|
#
4ef69160 |
| 15-May-2019 |
Anson Huang <anson.huang@nxp.com> |
dt-bindings: clock: imx8mq: Add SNVS clock
Add macro for the SNVS clock of the i.MX8MQ.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signe
dt-bindings: clock: imx8mq: Add SNVS clock
Add macro for the SNVS clock of the i.MX8MQ.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
Revision tags: v5.1, v5.1-rc7, v5.1-rc6, v5.1-rc5, v5.1-rc4, v5.1-rc3, v5.1-rc2, v5.1-rc1 |
|
#
010d5166 |
| 05-Mar-2019 |
Abel Vesa <abel.vesa@nxp.com> |
dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap. All the following clock ids are now decreased by 10 to keep the
dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap. All the following clock ids are now decreased by 10 to keep the numbering right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and all the following ids are updated accordingly.
Reported-by: Patrick Wildt <patrick@blueri.se> Fixes: 1cf3817b ("dt-bindings: Add binding for i.MX8MQ CCM") Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
Revision tags: v5.0 |
|
#
0c91c11c |
| 27-Feb-2019 |
Anson Huang <anson.huang@nxp.com> |
clk: imx8mq: add GPIO clocks to clock tree
i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-b
clk: imx8mq: add GPIO clocks to clock tree
i.MX8MQ has clock gate for each GPIO bank, add them into clock tree for GPIO driver to manage.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
Revision tags: v5.0-rc8, v5.0-rc7 |
|
#
45a359e8 |
| 15-Feb-2019 |
Abel Vesa <abel.vesa@nxp.com> |
dt-bindings: imx8mq-clock: Add the missing ARM clock
Add the missing ARM clock which will be used by cpufreq
Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutron
dt-bindings: imx8mq-clock: Add the missing ARM clock
Add the missing ARM clock which will be used by cpufreq
Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> [sboyd@kernel.org: Fixed numbering in dt header] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
Revision tags: v5.0-rc6, v5.0-rc5 |
|
#
202ce5af |
| 31-Jan-2019 |
Fabio Estevam <festevam@gmail.com> |
clk: imx8mq: Add support for the CLKO1 clock
Add the entry for the CLKO1 clock.
Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen B
clk: imx8mq: Add support for the CLKO1 clock
Add the entry for the CLKO1 clock.
Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|
Revision tags: v5.0-rc4, v5.0-rc3 |
|
#
c5b11ee9 |
| 16-Jan-2019 |
Guido Günther <agx@sigxcpu.org> |
dt-bindings: imx8mq: Number clocks consecutively
This fixes a duplicate use of 232 and numbers the clocks without holes.
Fixes: 1cf3817bf1f5 ("dt-bindings: Add binding for i.MX8MQ CCM") Signed-off-
dt-bindings: imx8mq: Number clocks consecutively
This fixes a duplicate use of 232 and numbers the clocks without holes.
Fixes: 1cf3817bf1f5 ("dt-bindings: Add binding for i.MX8MQ CCM") Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
show more ...
|
Revision tags: v5.0-rc2, v5.0-rc1, v4.20, v4.20-rc7, v4.20-rc6, v4.20-rc5 |
|
#
1cf3817b |
| 01-Dec-2018 |
Lucas Stach <l.stach@pengutronix.de> |
dt-bindings: Add binding for i.MX8MQ CCM
This adds the binding for the i.MX8MQ Clock Controller Module.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.c
dt-bindings: Add binding for i.MX8MQ CCM
This adds the binding for the i.MX8MQ Clock Controller Module.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
|