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5b9979fd |
| 22-Apr-2024 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
Add power domain IDs for the RZ/V2L (R9A07G054) SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytt
dt-bindings: clock: r9a07g054-cpg: Add power domain IDs
Add power domain IDs for the RZ/V2L (R9A07G054) SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20240422105355.1622177-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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4decd2e5 |
| 26-Jan-2022 |
Biju Das <biju.das.jz@bp.renesas.com> |
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0")
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
Define RZ/V2L (R9A07G054) Clock Pulse Generator Core Clock and module clock outputs, as listed in Table 7.1.4.2 ("Clock List r1.0") and also add Reset definitions referring to registers CPG_RST_* in Section 7.2.3 ("Register configuration") of the RZ/V2L Hardware User's Manual (Rev. 1.00, Nov. 2021).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220126211003.6675-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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