Use SysValue to store curlwp rather than curcpu. curlwp is acceessed
much more frequently, and this makes curlwp preemption-safe.

Garbage-collect the SWITCH_CONTEXT macro, since it now expands to
just "call_pal PAL_OSF1_swpctx".

Remove clause 3 and 4 from TNF licenses

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the v

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

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Fix a couple of problems when starting the idle lwp on secondary
cpus: Set curlwp, and allow interrupts before entering idle loop
(otherwise, IPI interrupts won't be handled on an idle cpu).

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

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No need to have code we don't use anymore.

We've fixed enough bugs that we can actually acquire the scheduler
lock, jump into the idle loop, and run user code! Yippee!

Loading the cpu_info value into the kgp for the new cpu isn't likely to work
very well.

Define the biglock perimeter for the Alpha port, and generally clean
up a bunch of the MP code. Still doens't work properly yet, this is
just a snapshot of work-in-progress.

- Remove a misguided attempt to use procs as idle contexts for secondary
processors. Instead, allocate separate idle PCBs for them (including
the primary -- don't use proc0's for its idle contex

- Remove a misguided attempt to use procs as idle contexts for secondary
processors. Instead, allocate separate idle PCBs for them (including
the primary -- don't use proc0's for its idle context).
- Use SysValue to store the cpu_info for each processor.

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Convert to traceback-friendly temporary labels.

Now that we have the kthread mechanism, massively clean up the way
additional processors are spun up on multiprocessor Alpha systems.
Now, each processor gets its own idle thread (the primary process

Now that we have the kthread mechanism, massively clean up the way
additional processors are spun up on multiprocessor Alpha systems.
Now, each processor gets its own idle thread (the primary processor
uses proc0). This idle thread is used in switch_exit(), rather than
explicitly referencing proc0.

Also, make `curproc', `fpcurproc', and `curpcb' per-cpu values. This
required some data structure rearrangement; cpu info is now statically
allocated in the BSS, rather than via malloc(), and cpu_softc is gone.
(Modeled somewhat after NetBSD/sparc's multiprocessor info structures.)

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Invalidate the TB and I-stream upon entry, and fix a typo in the wrkgp call.

First-cut at code to spin up secondary processors on a multiprocessor
Alpha system, conditional on MULTIPROCESSOR.

NOTE: This does not yet work completely. The secondary CPU begins the
boot process

First-cut at code to spin up secondary processors on a multiprocessor
Alpha system, conditional on MULTIPROCESSOR.

NOTE: This does not yet work completely. The secondary CPU begins the
boot process, but never makes it into the cpu spinup trampoline. This
is merely a snapshot of a work-in-progress.

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