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Remove hard requirement for "offset" property on Cortex-A5. This is not required w/ FDT.

Add l2cc support.

allow arml2cc to be used on Cortex-A5 if the "offset" property is specified

clean the a9 l2 cache before turning it on.

Allow l2cc base to gotten from device properties.

pl310 cache is PIPT

#include <arm/locore.h>

KASSERT -> KASSERTMSG

simplify cache range op

Don't "sync" atomic ops.
Do sync after each range op.

Make these compile with gcc4.1 and binutils 2.16

Invalidate the L2 cache before enabling it.

Add a missing mutex exit.

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup

Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead
but add a second argument to it to indicate whether the TLB/caches need to be
flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field
to see if the fixed can be skipped.
Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1)
or enabeld (bit = 0).

With these changes, the A9 MMU can use traverse caches to do MMU tablewalks
Also, make sure all memory has the shareable bit for the A9.

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Add L2 cache flush routines. (not yet enabled).

Don't disable the L2C is it isn't enabled.

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and on

Switch cortex_a9 back to need_ptesync = 1
Add code to disable the L2 cache on cortex-a9 (for now).
Add evcnt for all the fault types.
Move cache info in a structure and have one for the pcache and one for scache.
Probe L1/L2 caches properly for ARMv7

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Add "write-back" before Unified

Add driver to attach ARM PL210 L2 Cache Controller
arml2cc0 at armperiph0: ARM PL310 L2 r3p2 Cache Controller
arml2cc0: 256KB/32B 16-way L2 Unified cache