Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all c

Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().

Standardize on of_compatible_match() for driver matching, and adapt
all call sites.

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rnd_attach_source calls the callback itself now.

No need for every driver to explicitly call it to prime the pool.

Eliminate now-unused <sys/rndpool.h>.

Restore %# for PRIxBUSADDR

Use PRIxBUSADDR

Support SATA on TEGRA210

Thanks to jmcneill for help with this.

Trailing whitespace

Initialize CML1 clock

Register clocks with clk_attach

Pass clock provider's phandle to fdtbus_clock_controller_func.decode()
and update callers.

This allows to accomodate clock managers whose clocks are identified
directly by a clock instead of a pair

Pass clock provider's phandle to fdtbus_clock_controller_func.decode()
and update callers.

This allows to accomodate clock managers whose clocks are identified
directly by a clock instead of a pair (clock provider, index).

ok jmcneill@ on port-arm

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Add missing pointer <-> integer casts
Use PRI?64 to print uint64_t instead 'll?'

use CLK_GATE_SIMPLE

Tegra210 HDA support.

add SOC_THERM and TSENSOR clocks

More PCIe / XUSBPAD initialization goo for Tegra210.

Add clocks used by pcie

Disable debug again

USB works on Tegra X1 now.

More XUSB init. A USB3 memory stick seems to work now.

Disable debug

Add APBDMA clock

More XUSB init stuff.

add USB2_TRK and HSIC_TRK clocks

Initialize PLLE

Setup PLLU

Fix div calculation and utmip init params