Don't write a 1 to the read only RIRR bit in the IOAPIC redirection
register to fix "tlp0: filter setup and transmit timeout" observed
on Hyper-V VMs with the Legacy Network Adapter.

From OpenBSD vi

Don't write a 1 to the read only RIRR bit in the IOAPIC redirection
register to fix "tlp0: filter setup and transmit timeout" observed
on Hyper-V VMs with the Legacy Network Adapter.

From OpenBSD via PR kern/49323:

https://marc.info/?l=openbsd-cvs&m=146718035432599&w=2

| Modified files:
| sys/arch/amd64/amd64: ioapic.c
| sys/arch/amd64/include: i82093reg.h
|
| Log message:
| Don't write a 1 to the RIRR bit in the IOAPIC redirection register. This bit
| is R/O, and although it should not matter what value is written there,
| Hyper-V's emulated IOAPIC interprets a write of 1 in some unexpected way and
| subsequently blocks interrupt delivery. This primarily manifests itself as
| de(4) timeouts when using Hyper-V VMs with the "Legacy Network Adapter"
| interface.

Tested both amd64 and i386 on Client Hyper-V on Windows 10.

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x86: Add preliminary x2APIC support.

x2APIC is used only when x2APIC is enabled in BIOS/UEFI.
LAPIC ID is not supported above 256.

Move the virtual address of the LAPIC page out of the data segment on amd64
and i386. The old design was error-prone, and it didn't allow us to map the
data segment with large pages.

Now, the VA is

Move the virtual address of the LAPIC page out of the data segment on amd64
and i386. The old design was error-prone, and it didn't allow us to map the
data segment with large pages.

Now, the VA is allocated dynamically in the pmap bootstrap code, and entered
manually later. We go from using &local_apic to using *local_apic_va, and we
therefore need one more level of indirection in the asm code.

Discussed on tech-kern.

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Remove "struct device" from "struct pic", where it was only real
for ioapics and faked up for others. Add it to "struct ioapic_softc"
for now, until device/softc get split.
This required all typecast

Remove "struct device" from "struct pic", where it was only real
for ioapics and faked up for others. Add it to "struct ioapic_softc"
for now, until device/softc get split.
This required all typecasts between "struct pic" and "struct ioapic_softc"
to be replaced, I hope I got them all.
functionally tested on i386, compile-tested on xen, untested on amd64

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- pass intrframe by-pointer, not by-value.
- make i386 and xen use per-cpu interrupt stack.

xen part is reviewed by Manuel Bouyer.

The i82093 spec is unclear about it, but my assumption that the selected
ioapic register would stick across a read+write appears to be invalid
for some ioapics. So, select it again for the mask write.

Block level-triggered interrupts at the ioapic if they are deferred.
Avoids interrupt storms seen on some systems. Many thanks to
Stoned Elipot for testing.

Redirect some includes to x86/foo.h

New interrupt code. The basic idea behind it is to hide the differences
in interrupt controllers in struct pic, and try to keep as much
common code as possible. At the lowest (asm) level, this is don

New interrupt code. The basic idea behind it is to hide the differences
in interrupt controllers in struct pic, and try to keep as much
common code as possible. At the lowest (asm) level, this is done
with CPP macros.

The main structure is now struct intrsource, describing an established
interrupt line, of any kind (soft/hard local apic/legacy apic/IO apic).
For quick masking, there may be a maximum of 32 sources per CPU.
Sources can be assigned to any CPU in the MP case, though currently they
all go to the boot CPU.

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Merge Bill Sommerfeld's i386 MP branch. This code has some known
caveats, but works quite well in a lot of MP cases, and all
UP cases that I have tested. Parts of this will hopefully be
reworked in t

Merge Bill Sommerfeld's i386 MP branch. This code has some known
caveats, but works quite well in a lot of MP cases, and all
UP cases that I have tested. Parts of this will hopefully be
reworked in the not-too-distant future.

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