DHT Walnut: Fix failure to attach on-board pdcide(4) for cold boot.

U-Boot seems to initialize pdcide(4) to compatible mode. Therefore, we
need to reinitialize it to native-PCI mode in pci_conf_hook

DHT Walnut: Fix failure to attach on-board pdcide(4) for cold boot.

U-Boot seems to initialize pdcide(4) to compatible mode. Therefore, we
need to reinitialize it to native-PCI mode in pci_conf_hook(). Otherwise,
we will fail to configure IO registers for native-PCI mode during
PCI_NETBSD_CONFIGURE.

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Include missing opt_pci.h

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it is

PCI Extended Configuration stuff written by nonaka@:
- Add PCI Extended Configuration Space support into x86.
- Check register offset of pci_conf_read() in MD part. It returns (pcireg_t)-1
if it isn't accessible.
- Decode Extended Capability in PCI Extended Configuration Space.
Currently the following extended capabilities are decoded:
- Advanced Error Reporting
- Virtual Channel
- Device Serial Number
- Power Budgeting
- Root Complex Link Declaration
- Root Complex Event Collector Association
- Access Control Services
- Alternative Routing-ID Interpretation
- Address Translation Services
- Single Root IO Virtualization
- Page Request
- TPH Requester
- Latency Tolerance Reporting
- Secondary PCI Express
- Process Address Space ID
- LN Requester
- L1 PM Substates
The following extended capabilities are not decoded yet:
- Root Complex Internal Link Control
- Multi-Function Virtual Channel
- RCRB Header
- Vendor Unique
- Configuration Access Correction
- Multiple Root IO Virtualization
- Multicast
- Resizable BAR
- Dynamic Power Allocation
- Protocol Multiplexing
- Downstream Port Containment
- Precision Time Management
- M-PCIe
- Function Reading Status Queueing
- Readiness Time Reporting
- Designated Vendor-Specific

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Add support pci_intr_setattr.
Export non-inline version of pci api for modules (_MODULE is defined).
Fix definition of pc_conf_hook and pc_conf_interrupt.
Switch to using inlines instead of macros.
S

Add support pci_intr_setattr.
Export non-inline version of pci api for modules (_MODULE is defined).
Fix definition of pc_conf_hook and pc_conf_interrupt.
Switch to using inlines instead of macros.
Switch ibm4xx to use <powerpc/pci_machdep.h>

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Use <sys/foo.h> instead of <machine/foo.h> if such a file exists.
Don't assume <sys/cpu.h> includes <powerpc/subarch/cpu*.h>. Include it
explicitly.

struct device * -> device_t
struct cfdata * -> cfdata_t
split device/softc (CFATTACH_DECL_NEW)
use device_accessors and device_private
constify

Support PowerPC 405EX/EXr.
1. Add some new source and header files.
(MAL(split) and RGMII(new) relations for EMAC)
2. Create dcr4xx.h. Its moved from dcr405gp.h. Also remove dcr405xx.h.

Support PowerPC 405EX/EXr.
1. Add some new source and header files.
(MAL(split) and RGMII(new) relations for EMAC)
2. Create dcr4xx.h. Its moved from dcr405gp.h. Also remove dcr405xx.h.
3. intr.c supports MULTIUIC with virtual-irq. likes to oea.
support 32-virq/128-hwirq.
4. multiple emac support.
5. WALNUT and VIRTEX_* includes arch/powerpc/conf/files.ibm4xx.
6. WALNUT pci uses arch/powerpc/ibm4xx/pci/.

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pci_intr_setattr(), allows PCI interrupts to be marked MPSAFE on x86, and
other platforms if the code is added.

pci_intr_map(...)
pci_intr_setattr(pc, ih, PCI_INTR_MPSAFE, 1);
pci_intr_establish(...)

Bring ibm4xx interrupt code up to date:

- generic soft interrupts (ie. use powerpc/softintr.c)
- interrupt event counters (using the ones from powerpc/cpu.h:cpu_info
where appropriate)
- cleanup i

Bring ibm4xx interrupt code up to date:

- generic soft interrupts (ie. use powerpc/softintr.c)
- interrupt event counters (using the ones from powerpc/cpu.h:cpu_info
where appropriate)
- cleanup ibm4xx_intr.h, move implementation details to intr.c

Convert all affected evbppc platforms.

OK by simonb@, some points discussed with matt@

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Move pci_intr_map and pci_conf_interrupt functions to MD codes.
Change Max PCI devices from 5 to 31.

PCI_NETBSD_CONFIGURE should allocate (but not map) address space expansion
ROMS by default. Full discussion at
http://mail-index.netbsd.org/tech-kern/2005/12/16/0023.html
Closes PR kern/32467
Revie

PCI_NETBSD_CONFIGURE should allocate (but not map) address space expansion
ROMS by default. Full discussion at
http://mail-index.netbsd.org/tech-kern/2005/12/16/0023.html
Closes PR kern/32467
Reviewed by briggs@

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merge ktrace-lwp.

Copy PCI codes for IBM405GPx from evbppc/walnut/pci/{pchb.c,pci_machdep.c}.