fix hang at 4B microseconds (1h12 or so), and simplify part of the previous

fix time goes backwards problems on sparc.

there are a few things here:
- there's a race between reading the limit register (which clears
the interrupt and the limit bit) and increasing the latest

fix time goes backwards problems on sparc.

there are a few things here:
- there's a race between reading the limit register (which clears
the interrupt and the limit bit) and increasing the latest offset.
this can happen easily if an interrupt comes between the read and
the call to tickle_tc() that increases the offset (i obverved this
actually happening.)
- in early boot, sometimes the counter can cycle twice before the
tickle happens.

to handle these issues, add two workarounds:
- if the limit bit isn't set, but the counter value is less than
the previous value, and the offset hasn't changed, use the same
fixup as if the limit bit was set. this handles the first case
above.
- add a hard-workaround for never allowing returning a smaller
value (except during 32 bit overflow): if the result is less than
the last result, add fixups until it does (or until it would
overflow.)

the first workaround fixes general run-time issues, and the second
fixes issues only seen during boot.

also expand some comments in timer_sun4m.c and re-enable the sun4m
sub-microsecond tmr_ustolim4m() support (but it's always called with
at least 'tick' microseconds, so the end result is the same.)

show more ...

remove schedintr_4m(), and go back to only having the level 14
timer call statclock/schedclock. the randomness for this clock
makes the hardclock() call very jittery.

instead of this, trigger a sof

remove schedintr_4m(), and go back to only having the level 14
timer call statclock/schedclock. the randomness for this clock
makes the hardclock() call very jittery.

instead of this, trigger a softintr IPI at level 10 on non-primary
CPUs from the primary CPU's clock interrupt (at level 10.) this
cleans up the generic sparc timer code a little as well.

this makes the time goes backwards problem *much* less frequent,
but i still see it sometimes.

show more ...

- remove unused but set variables.
- use __USE() where necessary.
- remove useless 'volatile' markers

kd.c:consinit() might be wrong for old proms, but i've not
changed it really.

Fix more -fno-common fallout.

convert all the sparc drivers that attach on my ss20 to use device_t,
cfdata_t and CFATTACH_DECL_NEW().

fd/fdc could use better testing, but i'm pretty sure i got it right.

#include <sys/bus.h> instead of <machine/bus.h>.

use schedintr() (not schedintr_4m()) on MP or single CPU configurations.

rework the timer interrupt usage on MP sun4m systems a little. use
either schedintr() or schedintr_4m() and make sure we call hardclock()
and schedclock() appropriately. the level10 interrupt isn't

rework the timer interrupt usage on MP sun4m systems a little. use
either schedintr() or schedintr_4m() and make sure we call hardclock()
and schedclock() appropriately. the level10 interrupt isn't used much
for MP sun4m systems anymore..

now, besides crazy interrupts panics, sparc smp is functionaly again.

show more ...

add an explicit "bool mpsafe" to intr_establish(). only set it to true
for the sun4m timer/counter interrupts. this gets lev10/14 working again
on SMP systems, where those interrupts started taking

add an explicit "bool mpsafe" to intr_establish(). only set it to true
for the sun4m timer/counter interrupts. this gets lev10/14 working again
on SMP systems, where those interrupts started taking the kernel lock and
hanging...

show more ...

Ansify function definitions w/o arguments. Generated with sed.

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implemen

Interrupt handling changes, in discussion since February:

- Reduce available SPL levels for hardware devices to none, vm, sched, high.
- Acquire kernel_lock only for interrupts at IPL_VM.
- Implement threaded soft interrupts.

show more ...

convert to timecounters (from branch simonb-timecounters)

Drop trailing whitespace.

ANSIify. Same binary code is produced for GENERIC.MP + KGDB + DDB.

Uppercase CPU, plural is CPUs.

__KERNEL_RCSID()

Make this compile with only SUN4 defined.

Move schedintr() to clock.c and initialise schedhz in initclocks(), so
these are available to all timer implementations.

Make the schedintr() code common for all timers.

intr_establish() signature change: pass NULL for the `fast trap' argument.

Pass the `device class interrupt level' on to intr_establish() and use to
raise the ipl in the interrupt handlers to the appropriate level. This avoids
interrupt handler interference if one of the de

Pass the `device class interrupt level' on to intr_establish() and use to
raise the ipl in the interrupt handlers to the appropriate level. This avoids
interrupt handler interference if one of the devices actually interrupts at
a lower hardware level than the maximum level assined to a device class.

Based on code from Art Grabowski in openbsd.

show more ...

Move timer{match,attach}_mainbus() back into timer.c, since the `timer at
mainbus' configuration declaration is orthogonal to the configured SUN4[CM]
platform options.

The presence of the `timer at obio' attachment is independent of the
various CPU support settings.

Add trailing ; to CFATTACH_DECL.