| #
2b1d5ff7 |
| 14-Jun-2019 |
msaitoh <msaitoh@NetBSD.org> |
No functional change:
- Rename macros:
- ICR, LVT and MSIDATA can share the bit definitions. Remove redundant
definitions and use the common macros.
- Consistently use LAPIC_LVT_ for all loca
No functional change:
- Rename macros:
- ICR, LVT and MSIDATA can share the bit definitions. Remove redundant
definitions and use the common macros.
- Consistently use LAPIC_LVT_ for all local vector table's macro names.
- Use __BITS().
- Add definition for TSC-deadline (LAPIC_LVT_TMM_TSCDLT).
show more ...
|
| #
01a8a95c |
| 13-Jun-2019 |
msaitoh <msaitoh@NetBSD.org> |
Indent consistently. No functional change.
|
| #
7e86a133 |
| 13-Jun-2019 |
msaitoh <msaitoh@NetBSD.org> |
Modify LAPIC_LVT_CMCI's comment to be consistent with other LVT's.
No functional change.
|
| #
24f521dc |
| 28-Apr-2017 |
nonaka <nonaka@NetBSD.org> |
Added AMD extended APIC register space present definition.
|
| #
df3a552c |
| 22-Apr-2017 |
nonaka <nonaka@NetBSD.org> |
move LAPIC_MSR* to specialreg.h.
|
| #
64b9a7bf |
| 22-Apr-2017 |
nonaka <nonaka@NetBSD.org> |
Add x2APIC register definitions.
|
| #
b2b61444 |
| 17-Jul-2015 |
msaitoh <msaitoh@NetBSD.org> |
Indent. No functional change.
|
| #
fac81bf5 |
| 26-Jan-2013 |
dyoung <dyoung@NetBSD.org> |
Several registers and bitfields named IOAPIC_* actually belong to the
LAPIC, so rename them LAPIC_* and move to a more appropriate header
file.
|
| #
68334d1b |
| 20-Jan-2012 |
hannken <hannken@NetBSD.org> |
Revert revision 1.4 and change LAPIC_LEVEL_ASSERT / _MASK back to 0x4000.
According to "Intel 64 and IA-32 Architectures Software Developer's Manual"
Vol. 3, May 2011, Order Number: 325384-039US, Se
Revert revision 1.4 and change LAPIC_LEVEL_ASSERT / _MASK back to 0x4000.
According to "Intel 64 and IA-32 Architectures Software Developer's Manual"
Vol. 3, May 2011, Order Number: 325384-039US, Section 10.6.1:
LEVEL_ASSERT is bit #14, bit #13 is reserved.
With this change NetBSD now boots multiple processors under CentOS 6.2/kvm.
show more ...
|
| #
37c06c3a |
| 15-Nov-2010 |
cegger <cegger@NetBSD.org> |
add interrupt EAPIC register definitions
|
| #
07e7c0c3 |
| 09-Jan-2010 |
cegger <cegger@NetBSD.org> |
add LAPIC_MSR_ENABLE_x2 MSR. from murray@river-styx via port-amd64@
'...as documented in the Intel 64 and IA32 Architectures Software
Developers Manual 3A, chapter 10.5.1.'
|
| #
ce85d1b2 |
| 12-May-2008 |
ad <ad@NetBSD.org> |
Some defs to describe the IA32_APIC_BASE MSR.
|
| #
d4e5a836 |
| 09-May-2008 |
cegger <cegger@NetBSD.org> |
Buildfix: Remove duplicate #defines.
|
| #
8b6686ae |
| 09-May-2008 |
ad <ad@NetBSD.org> |
LAPIC_ID_MASK is 8 bits these days.
|
| #
ce099b40 |
| 28-Apr-2008 |
martin <martin@NetBSD.org> |
Remove clause 3 and 4 from TNF licenses
|
| #
fe9a3139 |
| 22-Jan-2008 |
joerg <joerg@NetBSD.org> |
Fix LAPIC_LEVEL_MASK and related defines.
|
| #
64dcc1f5 |
| 14-Nov-2007 |
joerg <joerg@NetBSD.org> |
Merge from jmcneill-pm:
Add some more defines from the spec. Remove some old ones not
existing in the current Intel Architecture Guide. Use some more
understandable names.
ANSIfy and use uintXX_t to
Merge from jmcneill-pm:
Add some more defines from the spec. Remove some old ones not
existing in the current Intel Architecture Guide. Use some more
understandable names.
ANSIfy and use uintXX_t to hurt my eyes less.
Further improve readability by exploiting __HAVE_TIMECOUNTER as
invariance on x86 platforms.
show more ...
|
| #
1e320906 |
| 14-Nov-2007 |
ad <ad@NetBSD.org> |
+LAPIC_DLMODE_EXTINT
|
| #
8375b2d9 |
| 26-Feb-2003 |
fvdl <fvdl@NetBSD.org> |
Move some files out of i386 into x86, so that they can be shared with
other ports.
|