dwcmmc: Add support for card detect using SDMMC_CDETECT register

Remember / use sc_verid

More SDIO stability and performance fixes

dwc_mmc fixes:
- Rockchip uses a different SDIO int bit, so take this into consideration
- Avoid unnecessary resets and always wait for resets to complete
- kpause instead of delay while holding s

dwc_mmc fixes:
- Rockchip uses a different SDIO int bit, so take this into consideration
- Avoid unnecessary resets and always wait for resets to complete
- kpause instead of delay while holding spinlock
- Do not attempt autostop for SD_IO_RW_EXTENDED commands
- Allow for sub-blklen byte counts for single block transfers

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Fix performance regression with previous

dwcmmc improvements:
- Use mmcpwrseq resources if available
- Only set 4- or 8-bit mode if specified in the dt properties
- Add quirk for implementations with inverted power enable logic
- Suppor

dwcmmc improvements:
- Use mmcpwrseq resources if available
- Only set 4- or 8-bit mode if specified in the dt properties
- Add quirk for implementations with inverted power enable logic
- Support switching signal voltage between 1.8V and 3.3V
- Fix a clock divider issue on Rockchip SoCs

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Add support for SDIO interrupts.

Simplify card detect

dwcmmc: set ciu clock rate rather than assuming fixed input rate

More or less a rewrite of dwc_mmc, based on awin_mmc, adding DMA support.

Dump registers on timeout and allow bus glue to override card detect func

build fix

- Simplify clock setup
- Add DWC_MMC_F_FORCE_CLK flag, which forces updating clock for each
command (apparently required by Rockchip)
- Let bus glue limit the max clk speed used

- Explicitly initialize CLKSRC register.
- Reset FIFO and DMA along with controller.
- Support chips with inverted PWREN logic.
- Enable RXDR and TXDR irqs.
- Set max clk based on supplied clock freq

- Explicitly initialize CLKSRC register.
- Reset FIFO and DMA along with controller.
- Support chips with inverted PWREN logic.
- Enable RXDR and TXDR irqs.
- Set max clk based on supplied clock freq.
- Use external clk control as well as internal divisor to set clock rates.
Requires bus glue to implement sc_set_clkdiv callback.

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add DesignWare SD/MMC controller driver