_C_LABEL() and _ASM_LABEL() are no longer useful in the "everything
is ELF" world. Eliminate use of them in amd64, arm64, armv7, i386,
macppc, mips64, and sparc64 code.

ok deraadt@ jca@ krw@

excuted -> executed

Split out the code that brings us out of HYP mode and the code that
initializes the MMU into its own functions and move them to locore.S.

ok patrick@

Make it possible to build a MULTIPROCESSOR kernel on armv7. While this
doesn't actually spin up any secondary CPUs, it does run. Mostly a cleanup
of <machine/cpu.h> along the lines of what I did ea

Make it possible to build a MULTIPROCESSOR kernel on armv7. While this
doesn't actually spin up any secondary CPUs, it does run. Mostly a cleanup
of <machine/cpu.h> along the lines of what I did earlier on arm64. Makes
armv7 use the MI mplock implementation and implements copyin32.

ok patrick@

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use virt instructions with clang instead of equivalent raw bytes

The Cortex-A17 TRM explicitly says that there is an intermediate table
walk cache and that its cache entries are associated with an ASID.
Our armv7 pmap doesn't use ASIDs and we only ever insert "glo

The Cortex-A17 TRM explicitly says that there is an intermediate table
walk cache and that its cache entries are associated with an ASID.
Our armv7 pmap doesn't use ASIDs and we only ever insert "global" page
table entries which match (and get flushed) regardless of the ASID.
The current ASID is specified vy the CONTEXTIDR register, which is
initialized to some "unknown" value. And on my hardware that value
isn't zero! So the intermediate table walk cache entries are tagged
with this unknown value. But our TLB flushes are done with ASID 0.
This means that the intermediate table walk cache entries are never
flushed because the ASID doesn't match. As a result the hardware may
look at the wrong page table page when looking up a translation.

So initialize CONTEXTIDR to zero before we initialize the first
level page table pointer, flush the TLB and enable the MMU. Fixes
the hangs previously seen on Cortex-A12/A17.

ok patrick@

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Replace CPWAIT with an isb instruction, which is the proper way to make sure
CP15 updates are visible. Also add an isb instruction before switching on
the MMU to make sure that all the MMU-related C

Replace CPWAIT with an isb instruction, which is the proper way to make sure
CP15 updates are visible. Also add an isb instruction before switching on
the MMU to make sure that all the MMU-related CP15 registers updates are
visible.

Makes booting on a Cortex-A12/A17 get a bit further.

ok drahn@, jsg@

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Split early startup code out of armv7_start.S into locore0.S. Adjust
link run so that this locore0.o is always at the start of the
executable. But randomize the link order of all other .o files in

Split early startup code out of armv7_start.S into locore0.S. Adjust
link run so that this locore0.o is always at the start of the
executable. But randomize the link order of all other .o files in the
kernel, so that their exec/rodata/data/bss segments land all over the
place. Note that this commit does not yet unmap the early bootcode
since this is not as easy as on arm64.

As a result, the internal layout of every newly build bsd kernel is
different from past kernels. Internal relative offsets are not known
to an outside attacker. The only known offsets are in the startup code,
which has been unmapped.

Ramdisk kernels cannot be compiled like this, because they are gzip'd.
When the internal pointer references change, the compression dictionary
bloats and results in poorer compression.

With guidance and ok deraadt@

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