_C_LABEL() and _ASM_LABEL() are no longer useful in the "everything
is ELF" world. Eliminate use of them in amd64, arm64, armv7, i386,
macppc, mips64, and sparc64 code.

ok deraadt@ jca@ krw@

remove cpu var from i386; removed from amd64 in 2015
ok daniel@

Recommit preparation for i386 Meltdown fix after OpenBSD 6.3 release.

- provide a cpu_softc for cpu_attach() etc.
- replace per PCB TSS with per CPU TSS

The first change prepares for cpu_info being

Recommit preparation for i386 Meltdown fix after OpenBSD 6.3 release.

- provide a cpu_softc for cpu_attach() etc.
- replace per PCB TSS with per CPU TSS

The first change prepares for cpu_info being embedded in a
cpu_full_info. Therefore during autoconf/cpu_attach we hand down
a softc.

The second change removes the per PCB TSS. We now have one TSS per
CPU, thus in cpu_switchto() we only have to patch the ring 0 stack
pointer instead of loading a new TSS. This also allows for cleaning
up the GDT, so we only have a single slot for the TSS.

from hshoexer@; OK deraadt@

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iBackout the preparations for fixing Meltdown on i386. The task was
only halfway done and the current state does not help anybody. For
OpenBSD 6.3 release go back to the original code before 2018/0

iBackout the preparations for fixing Meltdown on i386. The task was
only halfway done and the current state does not help anybody. For
OpenBSD 6.3 release go back to the original code before 2018/03/13.
This gives us a stable release and the changes will come back later.
discussed with guenther@ deraadt@ hshoexer@

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Preparation for i386 Meltdown fix:

- provide a cpu_softc for cpu_attach() etc.
- replace per PCB TSS with per CPU TSS

The first change prepares for cpu_info being embedded in a
cpu_full_info. Ther

Preparation for i386 Meltdown fix:

- provide a cpu_softc for cpu_attach() etc.
- replace per PCB TSS with per CPU TSS

The first change prepares for cpu_info being embedded in a
cpu_full_info. Therefore during autoconf/cpu_attach we hand down
a softc.

The second change removes the per PCB TSS. We now have one TSS per
CPU, thus in cpu_switchto() we only have to patch the ring 0 stack
pointer instead of loading a new TSS. This also allows for cleaning
up the GDT, so we only have a single slot for the TSS.

from hshoexer@; OK deraadt@

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suppress local symbols in mptramp. Matches a similar diff in
acpi_wakecode.s that was committed previously.

Tested MP boot, un-zzz, un-ZZZ, no issues seen.

Catch up with changes made on amd64 (kettenis@):

Generating mixed 16-bit/32-bit/64-bit code with clang's integrated
assembler is a bit tricky. It supports the .code16, .code32 and
.code64 directive

Catch up with changes made on amd64 (kettenis@):

Generating mixed 16-bit/32-bit/64-bit code with clang's integrated
assembler is a bit tricky. It supports the .code16, .code32 and
.code64 directives. But it doesn't know about the data16/data32 and
addr16/addr32 instruction prefixes. Instead it tries to determine
those from the instruction opcode. It mostly succeeds, but there are
a couple of corner cases where clang will generate the "addr32" form
where gas generates the "addr16" form in .code16 segments. That
should be no problem (and just waste a couple of bytes), but it makes
comparing the generated code a bit difficult.

Allow the trampoline code to be compiled with both. For clang #define
away the addr32 prefix and avoid using the data32 prefix by using a
mnemonic that explicitly encodes the size of the operand. Add a few
addr32 prefixes in .code16 blocks to reduce the differences between
code generated by clang and gas.

ok deraadt@

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When determining whether or not to hatch into PAE mode, use the cpu_pae
flag variable instead of checking some pointer assignment made earlier
in pae_bootstrap.

ok guenther

remove some ancient debugging code

ok deraadt@

Split i386 mp hatch trampoline into code and data pages, and protect each
with proper W^X policy. The same thing was done for amd64 late last year,
catching i386 up now. Diff has been in snaps for a

Split i386 mp hatch trampoline into code and data pages, and protect each
with proper W^X policy. The same thing was done for amd64 late last year,
catching i386 up now. Diff has been in snaps for a few days with no
reported fallout.

ok deraadt@

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Only enable PAE if the CPU we're running on has NX support. Without NX
support we're only wasting memory on the larger PAE page tables without
any real benefit. This allows some simplifications of

Only enable PAE if the CPU we're running on has NX support. Without NX
support we're only wasting memory on the larger PAE page tables without
any real benefit. This allows some simplifications of the low-level
assembly code.

ok mlarkin@, deraadt@

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Enable the NX bit and use it in the PAE pmap code. PAE is still disabled
while we're chasing at least one remaining bug.

ok mlarkin@, deraadt@

Bring PAE code back to life, in a different form. This diff (via bluhm then
to deraadt, then myself) brings the PAE pmap on i386 (not touched in any
significant way for years) closer to the current n

Bring PAE code back to life, in a different form. This diff (via bluhm then
to deraadt, then myself) brings the PAE pmap on i386 (not touched in any
significant way for years) closer to the current non-PAE pmap and allows
us to take a big next step toward better i386 W^X in the kernel (similar to
what we did a few months ago on amd64). Unlike the original PAE pmap, this
diff will not be supporting > 4GB physical memory on i386 - this effort is
specifically geared toward providing W^X (via NX) only.

There still seems to be a bug removing certain pmap entries when PAE is
enabled, so I'm leaving PAE mode disabled for the moment until we can
figure out what is going on, but with this diff in the tree hopefully
others can help.

The pmap functions now operate through function pointers, due to the need
to support both non-PAE and PAE forms. My unscientific testing showed
less than 0.3% (a third of a percent) slowdown with this approach during
a base build.

Discussed for months with guenther, kettenis, and deraadt.

ok kettenis@, deraadt@

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Don't use the first 64KB for anything, including tramps. Move tramps and
hibernate goo up after 64KB to avoid posible corruption by buggy BIOS SMM
code. Diff also ensures the first 64KB doesn't get h

Don't use the first 64KB for anything, including tramps. Move tramps and
hibernate goo up after 64KB to avoid posible corruption by buggy BIOS SMM
code. Diff also ensures the first 64KB doesn't get handed to UVM either.

ok deraadt@, tested by many with no regressions reported

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Don't index cpu_info by apic id, but by device unit number instead. Recent
Intel CPUs come up with apic id's >= 32, even on systems with less than 32
logical CPUs.

ok krw@, marco@; tested by deraad

Don't index cpu_info by apic id, but by device unit number instead. Recent
Intel CPUs come up with apic id's >= 32, even on systems with less than 32
logical CPUs.

ok krw@, marco@; tested by deraadt@

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Switch away from using -traditional-cpp to iso/ansi cpp for asm files.
More architectures hopefully to follow.
ok kettenis@

Free TSS on the stack of the dead process.

In order to do that we have to remove all sleeping parts: sleeping
memory allocation and a sleeping lock. Thus we're moving this code
to the spinning lock

Free TSS on the stack of the dead process.

In order to do that we have to remove all sleeping parts: sleeping
memory allocation and a sleeping lock. Thus we're moving this code
to the spinning lock (mutex) and getting rid of the GDT grow code.
Downside is that now we're pre-allocating 64kb of memory per CPU
from the start, but this might be optimized in future.

This also unifies GDT code and MAXGDTSIZ define across i386 and amd64.

With help from mickey.

ok toby, art

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First pass at removing clauses 3 and 4 from NetBSD licenses.

Not sure what's more surprising: how long it took for NetBSD to
catch up to the rest of the BSDs (including UCB), or the amount of
code t

First pass at removing clauses 3 and 4 from NetBSD licenses.

Not sure what's more surprising: how long it took for NetBSD to
catch up to the rest of the BSDs (including UCB), or the amount of
code that NetBSD has claimed for itself without attributing to the
actual authors.

OK deraadt@

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Make context switching much more MI:
- Move the functionality of choosing a process from cpu_switch into
a much simpler function: cpu_switchto. Instead of having the locore
code walk the run q

Make context switching much more MI:
- Move the functionality of choosing a process from cpu_switch into
a much simpler function: cpu_switchto. Instead of having the locore
code walk the run queues, let the MI code choose the process we
want to run and only implement the context switching itself in MD
code.
- Let MD context switching run without worrying about spls or locks.
- Instead of having the idle loop implemented with special contexts
in MD code, implement one idle proc for each cpu. make the idle
loop MI with MD hooks.
- Change the proc lists from the old style vax queues to TAILQs.
- Change the sleep queue from vax queues to TAILQs. This makes
wakeup() go from O(n^2) to O(n)

there will be some MD fallout, but it will be fixed shortly.
There's also a few cleanups to be done after this.

deraadt@, kettenis@ ok

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Revert PAE pmap for now, until the strange bug is found. This stops
the freezes many of us are seeing (especially on amd64 machines running
OpenBSD/i386).

Much testing by nick@ (as always - thanks!

Revert PAE pmap for now, until the strange bug is found. This stops
the freezes many of us are seeing (especially on amd64 machines running
OpenBSD/i386).

Much testing by nick@ (as always - thanks!), hugh@, ian@, kettenis@
and Sam Smith (s (at) msmith (dot) net).

Requested by, input from, and ok deraadt@ ok art@, kettenis@, miod@

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Fix some more "is is"s. ok otto@.

implement separate PAE pmap that allows access to 64g of physmem
if supported by the cpu(s). currently not enabled by default and
not compiled into ramdisks. this grows paddr_t to 64bit but yet
leave

implement separate PAE pmap that allows access to 64g of physmem
if supported by the cpu(s). currently not enabled by default and
not compiled into ramdisks. this grows paddr_t to 64bit but yet
leaves bus_addr_t at 32bits. measures are taken to favour dmaable
memory allocation from below 4g line such that buffer cache is
already allocated form below, pool backend allocator prefers lower
memory and then finally bounce buffers are used as last resort.
PAE is engaged only if global variable cpu_pae is manually set
to non-zero and there is physical memory present above 4g.
simplify pcibios address math to use u_long as we always will
be in the 32bit space.

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trailing tabs nomore

white space vs tabs; no binary change

optimise one more jmp out of the idle loop; toby@ marco@ ok