Rename `ci_intrdepth' to `ci_idepth'.

ok jsg@, visa@

Remove unused RM7000 ICR handling.

Implement splassert() on mips64.

Adjust interrupt priority levels on mips64 so that priorities
of soft interrupts are lower than priorities of hard interrupts.
This allows the delivery of hard interrupts while soft interrupts
are ma

Adjust interrupt priority levels on mips64 so that priorities
of soft interrupts are lower than priorities of hard interrupts.
This allows the delivery of hard interrupts while soft interrupts
are masked.

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Move intr_barrier(9) to the platform level so that it can be customized.

Include header <sys/evcount.h> where event counters are used, so that
header <machine/intr.h> can eventually stop including it on octeon.

Declare ci_ipl volatile to prevent the compiler from optimizing
or reordering accesses to the variable. Assume that the assembler
preserves the correct sequence of instructions, which allows the
remo

Declare ci_ipl volatile to prevent the compiler from optimizing
or reordering accesses to the variable. Assume that the assembler
preserves the correct sequence of instructions, which allows the
removal of the explicit noreorder/reorder toggles from the C code.

With ci_ipl being volatile, drop mips_sync() calls that follow
the accesses of the variable. The sync is redundant as a compiler
barrier. In addition, the MIPS64 CPU designs should not need the
sync for pipeline or write buffer control. According to miod@,
the use of the instruction is a carryover from code targeting
early MIPS designs that lack tight integration with the cache
and write buffer.

Discussed with and testing help from miod@.
Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000,
R4400, R8000, R10000 and R16000.

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Define register_splx_handler() in one place.

Remove RM7000/RM9000-specific performance counter code. It originates
from PMON2000 and has not been enabled on OpenBSD.

Suggested by and ok miod@ (after seeing a quad_t cleanup patch of mine)

Rename mips64's trap_frame into trapframe.

For coherency with other archs and in order to use it in MI code.

ok visa@, tobiasu@

intr_barrier(9) for loongson, octeon and sgi.

implement atomic operations using ll/sc, and convert rw_cas and callers of the
pre-existing atomics to match.

tested on sgi (octane) and octeon (erl)
ok miod@ dlg@

Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs,
which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the
goriest md details, which are only of interes

Split ever-growing mips <machine/cpu.h> into what 99% of the kernel needs,
which will remain in <machine/cpu.h>, and a new mips_cpu.h containing only the
goriest md details, which are only of interest to a handful set of files; this
is similar in spirit to what alpha does, but here <machine/cpu.h> does not
include the new file.

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Add a few more coprocessor 0 cause and config registers defines.

Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions of
such statements with it.

Get rid of evcount's support for arranging counters in a tree
hierarchy. Everything attached to a single root node anyway, so at
best we had a bush.

"i think it is good" deraadt@

more cleanup to cope with the change that tries to make proc.h not act
like it is everything.h
ok tedu

Since we don't use the saved ipl in pcb anymore, remove it from the struct
layout.

Make trapdebug code MP-safe.

Make interrupt depth counters per-cpu.

atomic counter increment for SMP.
ok jsing@

Now IPI can interrupt to clock interrupt handler.
It prevents deadlock with TLB shootdown and clock interrupt.
ok miod@

Fix compile error in uniprocessor kernel.
ok jsing@

Correct cording style.
ok jsing@

mplock, rw_cas implemented
ok miod@