On Allwinner D1, the SBI call to schedule timer interrupts doesn't work.
Instead we have to use one of the timers integerated on the SoC that
triggers an external interrupt. Add the appropriate driv

On Allwinner D1, the SBI call to schedule timer interrupts doesn't work.
Instead we have to use one of the timers integerated on the SoC that
triggers an external interrupt. Add the appropriate driver and change
the MD clock code to hook it up.

ok cheloha@, jca@

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Move fdt attachment into sys/conf/files.conf instead of duplicating it on
an MD basis.

ok patrick@

Add stfrng(4), a driver for the random number generator on the JH7110 SoC.

ok joel@, jca@

Remove dead code.

Add support for the PCIe controller on the JH7110 SoC.

MSIs don't work reliably so these are disabled for now. The stfpcie(4)
driver is based on preliminary device tree bindings that might still
ch

Add support for the PCIe controller on the JH7110 SoC.

MSIs don't work reliably so these are disabled for now. The stfpcie(4)
driver is based on preliminary device tree bindings that might still
change.

ok patrick@

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Add stftemp(4), a driver for the temperature sensor integrated on the
StarFive JH7100 SoC.

ok jsg@

Add stfpinctrl(4), a driver for the pinctrl/gpio block found on the
StarFive JH7100 SoC.

ok jsg@

Add stfclock(4), a driver for the clock controller found on the StarFive
JH7100 SoC.

ok jsg@

Add sfgpio(4), a driver for the GPIO controller found on the
SiFive FU740 SoC.

ok jca@

Add mpfgpio(4), a driver for the PolarFire SoC MSS GPIO controller.

Feedback and OK kettenis@

Add mpfiic(4), a driver for the PolarFire SoC MSS I2C controller.

OK kettenis@

Add mpfclock(4), a driver for the PolarFire SoC MSS clock controller.

OK kettenis@

cleanup conf.c, and bring in wd(4) support
ok kettenis

sync maxusers with other 64bits architectures. ok kettenis@, deraadt@.

basic radeondrm / X support for riscv64. Ok kettenis@

- add wscons devices
- build radeondrm and add MD uvm bits to support it.

Add sfclock(4), a driver for the PRCI (Power Reset Clocking Interrupt) block
of the SiFive FU740 SoC.

ok deraadt@

Add a few more drivers that people might need.
ok drahn

enable nvme, a few pci devices and a bunch of usb stuff.
will cleanup later, enabling additional systems.

Serial driver for SiFive Unmatched (U74) based on dev/fdt/amluart.c
console input and output working, userland input and output at least
partially working.
'commit that driver, further improvements c

Serial driver for SiFive Unmatched (U74) based on dev/fdt/amluart.c
console input and output working, userland input and output at least
partially working.
'commit that driver, further improvements can happen in-tree' deraadt@

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Add PCI support.

ok deraadt@

add OpenBSD rcs ids

enable dwmmc(4)

The StarFive JH7100 SoC found on the BeagleV beta boards has most of
its peripherals hooked up through a bus that doesn't maintain cache
coherency. So in order to use DMA we will need to flush the L

The StarFive JH7100 SoC found on the BeagleV beta boards has most of
its peripherals hooked up through a bus that doesn't maintain cache
coherency. So in order to use DMA we will need to flush the L2 caches
before/after a DMA tranfer. Add a driver for the L2 cache controller
for these SoCs and infrastructure to do the necessary cache maintenance.
Since this particular L2 cache controller needs physical addresses, this
makes the bus_dma(4) code deviate from its arm64 counterpart.

ok drahn@

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rename trap.S exception.S and trap_machdep.c trap.c to match other archs
ok kettenis@

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on

The clock on RISC-V is architectural, so we really don't need the
whole abstraction layer to support multiple timers. And we don't
really need a separate driver. Replace timer(4) with code based on
the powerpc64 implementation of the randomized statclock code.

Fixes hangs seen on real hardware.

ok jsg@, drahn@

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