Fix writing the prefetchable mmio window base/limit.

ok patrick@

Enable MSIs on RK3588. We have a U-Boot package with device trees that
work now.

ok patrick@

Implement Multiple Message MSI support on arm64. As on amd64 this is
experimental code to assis qwx(4) development. Currently this only works
on systems that use agintcmsi(4) as the MSI controller

Implement Multiple Message MSI support on arm64. As on amd64 this is
experimental code to assis qwx(4) development. Currently this only works
on systems that use agintcmsi(4) as the MSI controller combined with the
dwpcie(4) Hots/PCIe bridge.

ok patrick@

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Encode the device tree node in the pci tag like we do in aplpcie(4) so that
PCI device drivers can have access to device tree properties, e.g. to allow
qwx(4) to retrieve the calibration variant.

ok

Encode the device tree node in the pci tag like we do in aplpcie(4) so that
PCI device drivers can have access to device tree properties, e.g. to allow
qwx(4) to retrieve the calibration variant.

ok kettenis@

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avoid use after free
ok miod@ millert@

Add support for (one of) the PCIe controllers on the RK3588 SoC. Since
MSIs don't work (yet) on this SoC, implement support for legacy interrupts
for the Rockchip SoCs. Also drop the restrictions o

Add support for (one of) the PCIe controllers on the RK3588 SoC. Since
MSIs don't work (yet) on this SoC, implement support for legacy interrupts
for the Rockchip SoCs. Also drop the restrictions on the bus number range
as the device tree I'm using has bus numbers start at 64 for the controller
in question.

ok patrick@, dlg@`

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Fix config space access for the root bus of a dwpcie(4) controller when
the root bus number isn't zero.

ok patrick@, dlg@

Enable power management for PCI devices.

ok kettenis@

Enable MSI if the node contains an msi-map, like we already do in pciecam(4).
This will make MSIs work on the Lenovo x13s as soon as an updated device tree
is installed.

Discussed with kettenis@

Call dwpcie_link_config() when initializing the RK3568 PCIe controllers.
This makes sure the PCIe link runs at the maximum possible speed.

Prompted by a diff from dlg@, who also tested this alternat

Call dwpcie_link_config() when initializing the RK3568 PCIe controllers.
This makes sure the PCIe link runs at the maximum possible speed.

Prompted by a diff from dlg@, who also tested this alternative diff.

ok dlg@

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keep match strings sorted

Attach Baikal-M PCIe

https://github.com/Elpitech/baikal-m-linux-kernel/search?q=bm1000-pcie
Tested on ET-101-MB

Initial diff from Slava Voronzoff
Feedback OK kettenis patrick

Add code to bring up the PCIe controller on the RK356x.

ok dlg@

Add some minimal initialization code for rk356x such that the kernel
doesn't hang.

ok millert@, dlg@

Implement support for the (optional) MSI controller of Synopsys Designware
PCIe host bridge. This MSI controller is quite retarded since it maps all
MSIs to a single hardware interrupt. So it doesn

Implement support for the (optional) MSI controller of Synopsys Designware
PCIe host bridge. This MSI controller is quite retarded since it maps all
MSIs to a single hardware interrupt. So it doesn't really offer any
benefit over using classic INTx interrupts. Unfortunately we need to use
it on Amlogic SoCs since the PCIe device interrupt doesn't seem to work
correctly when configured as a level triggered interrupt and the workaround
of configuring it as an edge triggered interrupt causes problems when using
multiple disks connected to ahci(4) on the ODROID-HC4.

ok patrick@

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Add support for the PCIe controller on the Qualcomm SC8280XP. Thankfully
UEFI already initializes those, so we can simply just make use of that.

That said, the ctrl/dbi region isn't the first in th

Add support for the PCIe controller on the Qualcomm SC8280XP. Thankfully
UEFI already initializes those, so we can simply just make use of that.

That said, the ctrl/dbi region isn't the first in the register list, so
instead try and look it up first and use it if available. Furthermore,
the ATU region isn't part of the ctrl/dbi region, so if we are able to
retrieve a separate reg for the ATU, use that instead. Some reshuffling
is necessary to make that work.

Tested on my Lenovo x13s and the MacchiatoBin
ok kettenis@

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Add (minimal) support for the RK3568 PCIe controller. This relies on
the firmware to do most of the hardware initialization; the driver
basically only sets up the address translation unit to match t

Add (minimal) support for the RK3568 PCIe controller. This relies on
the firmware to do most of the hardware initialization; the driver
basically only sets up the address translation unit to match the
configuration specified in the device tree.

ok patrick@

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Constify struct cfattach.

ok visa@ a long time ago, ok patrick@

Make sure we translate prefetchable mmio space as well.

From Mickael Torres.

While it seems like we can choose any I/O virtual address for peripheral
devices, this isn't really the case. It depends on the bus topology of
how devices are connected. In the case of PCIe, devic

While it seems like we can choose any I/O virtual address for peripheral
devices, this isn't really the case. It depends on the bus topology of
how devices are connected. In the case of PCIe, devices are assigned
addresses (in PCI BARs) from the PCI address spaces. Now if we take an
address from one of these address spaces for our IOVA, transfers from
from a PCI device to that address will terminate inside of the PCI bus.
This is because from the PCI buses' point-of-view, the address we chose
is part of its address space. To make sure we don't allocate addresses
from there, reserve the PCI addresses in the IOVA.

Note that smmu(4) currently gives each device its own IOVA. So the PCI
addresses will be reserved only in IOVA from PCI devices, and only the
addresses concerning the PCI bus it is connected to will be reserved.
All other devices behind an smmu(4) will not have any changes to their
IOVA.

ok kettenis@

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Add support for the 64-bit prefetchable memory window.

ok patrick@

Enable 32-bit I/O addressing. This gets rid of the io address conflict
messages on the HiFive Unmatched.

ok patrick@

Simplify the way we handle PCI configuration space access. Instead of
splitting the configuration space access window in a part for type 0 and
a part for type 1 commands, use a single window. The c

Simplify the way we handle PCI configuration space access. Instead of
splitting the configuration space access window in a part for type 0 and
a part for type 1 commands, use a single window. The code already flips
between type 0 and type 1 so there is no benefit in having this complication.

Fixes the PCIe host bridge on the SiFive FU740 SoC.

ok drahn@, patrick@

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Enable dwpcie(4) and add support for the PCIe host bridge found on the
SiFive FU740 SoC.

ok drahn@

Rename some MD structs by giving them an architecture-neutral name in
preparation for sharing PCIe host bridge drivers between arm64 and riscv64.

ok mpi@, mlarkin@, patrick@