Implement resetting the PHY via a GPIO pin, like in fec(4). This helps
enable the PHY on the Raspberry Pi 5.

ok kettenis@

Replace a bunch of (1 << 31) with (1U << 31)

Unbreak, don't assume we always hold the NET_LOCK

After net/if.c:rev 1.661 ifioctl() doesn't take the net lock any more
around SIOCGIFMEDIA and SIOCSIFMEDIA, which broke cad_ioctl().
The same was al

Unbreak, don't assume we always hold the NET_LOCK

After net/if.c:rev 1.661 ifioctl() doesn't take the net lock any more
around SIOCGIFMEDIA and SIOCSIFMEDIA, which broke cad_ioctl().
The same was already true about SIOCGIFSFFPAGE. Only release/reacquire
the net lock if warranted.

Input mvs@, ok miod@ mvs@ bluhm@

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Make cad(4) handle rxr ioctl.

Prevent deadlock in cad_down()

Introduce an rwlock to serialize cad(4) ioctl operations so that
cad_down() can release NET_LOCK() temporarily when invoking barriers.
This releasing prevents a possib

Prevent deadlock in cad_down()

Introduce an rwlock to serialize cad(4) ioctl operations so that
cad_down() can release NET_LOCK() temporarily when invoking barriers.
This releasing prevents a possible deadlock with the taskq barrier.
The deadlock was pointed out by witness(4).

In addition, release NET_LOCK() when allocating memory in cad_up()
to reduce the risk of ill effects.

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cad(4): Disable unused priority queues

The GEMs on the PolarFire Soc implement four Rx queues and four
Tx queues for prioritizing traffic. All the queues are in a pseudo
active state after reset. Th

cad(4): Disable unused priority queues

The GEMs on the PolarFire Soc implement four Rx queues and four
Tx queues for prioritizing traffic. All the queues are in a pseudo
active state after reset. The driver uses only queues with index 0.
Disable the rest to avoid DMA errors.

Tested on a SiFive FU740 by jca@, Microchip PolarFire SoC and
Xilinx Zynq-7000 by me.

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Change driver class from DV_DULL to DV_IFNET, so that it can be recognized
as boot interface when doing netboot. This makes auto install/upgrade work.

ok kettenis@ visa@

Create DMA maps with 64-bit capability when appropriate.

OK kettenis@

Use config register to determine if 64-bit DMA is available.

Suggested by and OK kettenis@

match on sifive,fu540-c000-gem

used by the hifive unmatched device tree in mainline linux and u-boot
ok visa@

cad: Implement 64-bit DMA mode

This lets the driver utilize 64-bit DMA on hardware that supports it.

Currently, riscv64 does not constrain DMA-reachable memory to the 32-bit
range. This caused memo

cad: Implement 64-bit DMA mode

This lets the driver utilize 64-bit DMA on hardware that supports it.

Currently, riscv64 does not constrain DMA-reachable memory to the 32-bit
range. This caused memory errors with cad(4) on machines that have RAM
above 4GB in the physical address space.

Prompted by Mickael Torres

OK kettenis@

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Remove an unused struct.

Match sifive,fu740-c000-gem so that device is detected on Unmatched.
pointed out by jsg@

Add cad(4), a driver for Cadence GEM.

This initial revision targets the Zynq-7000, where the GEM implements
single transmit and receive queues with 32-bit DMA addresses. The driver
uses receive chec

Add cad(4), a driver for Cadence GEM.

This initial revision targets the Zynq-7000, where the GEM implements
single transmit and receive queues with 32-bit DMA addresses. The driver
uses receive checksum offload, but transmit checksum offload is disabled
because of a hardware quirk. Also, the hardware's receive path is prone
to getting stuck if input cannot be handled quickly enough. The driver
attempts to recover by restarting the receiver when no input has been
seen for a while.

OK kettenis@

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