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80663c26 |
| 10-Jul-2023 |
patrick <patrick@openbsd.org> |
The changes to the register layout affect the interrupt status/ack registers as well. Make use of these, otherwise it might lead to an interrupt flood.
ok kettenis@
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671f311c |
| 05-Mar-2023 |
patrick <patrick@openbsd.org> |
Mask off IPL flags before storing the IPL for an interrupt.
ok kettenis@ jmatthew@
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755066eb |
| 04-Mar-2023 |
kettenis <kettenis@openbsd.org> |
Turns out the RK3566 has a different value in the GPIO_VER_ID register than advertised in the RK3568. This value is present in the Linux driver and implies the new register layout. So handle both v
Turns out the RK3566 has a different value in the GPIO_VER_ID register than advertised in the RK3568. This value is present in the Linux driver and implies the new register layout. So handle both values. This makes GPIOs on the RK3566 actually work.
ok patrick@
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78bc23e3 |
| 26-Feb-2023 |
kettenis <kettenis@openbsd.org> |
Modern Rockchip SoCs, such as the RK356x and RK3588, use a different register layout where the upper 16 bits decide which of the lower 16 bits apply when writing to a register. Handle this new varia
Modern Rockchip SoCs, such as the RK356x and RK3588, use a different register layout where the upper 16 bits decide which of the lower 16 bits apply when writing to a register. Handle this new variant.
ok patrick@
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9fdf0c62 |
| 24-Oct-2021 |
mpi <mpi@openbsd.org> |
Constify struct cfattach.
ok visa@ a long time ago, ok patrick@
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452daaed |
| 17-Jul-2020 |
patrick <patrick@openbsd.org> |
Re-work intr_barrier(9) on arm64 to remove layer violation. So far we have stored the struct cpu_info * in the wrapper around the interrupt handler cookie, but since we can have a few layers inbetwe
Re-work intr_barrier(9) on arm64 to remove layer violation. So far we have stored the struct cpu_info * in the wrapper around the interrupt handler cookie, but since we can have a few layers inbetween, this does not seem very nice. Instead have each and every interrupt controller provide a barrier function. This means that intr_barrier(9) will in the end be executed by the interrupt controller that actually wired the pin to a core. And that's the only place where the information is stored.
ok kettenis@
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789e88a4 |
| 14-Jul-2020 |
patrick <patrick@openbsd.org> |
Extend the interrupt API on arm64 and armv7 to be able to pass around a struct cpu_info *. From a driver point of view the fdt_intr_establish_* API now also exist same functions with a *_cpu suffix.
Extend the interrupt API on arm64 and armv7 to be able to pass around a struct cpu_info *. From a driver point of view the fdt_intr_establish_* API now also exist same functions with a *_cpu suffix. Internally the "old" functions now call their *_cpu counterparts, passing NULL as ci. NULL will be interpreted as primary CPU in the interrupt controller code.
The internal framework for interrupt controllers has been changed so that the establish methods provided by an interrupt controller function always takes a struct cpu_info *.
Some drivers, like imxgpio(4) and rkgpio(4), only have a single interrupt line for multiple pins. On those we simply disallow trying to establish an interrupt on a non-primary CPU, returning NULL.
Since we do not have MP yet on armv7, all armv7 interrupt controllers do return NULL if an attempt is made to establish an interrupt on a different CPU. That said, so far there's no way this can happen. If we ever gain MP support, this is a reminder that the interrupt controller drivers have to be adjusted.
Prompted by dlg@ ok kettenis@
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e8c4db4a |
| 25-Apr-2020 |
kettenis <kettenis@openbsd.org> |
Remove redundant bit masking.
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565062e8 |
| 07-Apr-2020 |
kettenis <kettenis@openbsd.org> |
Fix off-by-one in check for valid pin numbers and use the existing #define in the check.
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80ce69e8 |
| 11-May-2019 |
patrick <patrick@openbsd.org> |
Implement interrupt controller functionality in the Rockchip GPIO driver. This allows us to use the fusbtc(4) interrupt on the RockPro64.
ok kettenis@
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acb3c9fc |
| 06-May-2017 |
kettenis <kettenis@openbsd.org> |
Add rkgpio(4), a driver to handle GPIOs on Rockchip SoCs.
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