Revision tags: v8.1.4, v7.2.8 |
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#
60db7a03 |
| 20-Dec-2023 |
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> |
docs/system/riscv: document acpi parameter of virt machine
Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI table generation. Add it to the documentation.
Fixes: 168b8c29cedb
docs/system/riscv: document acpi parameter of virt machine
Since QEMU v8.0.0 the RISC-V virt machine has a switch to disable ACPI table generation. Add it to the documentation.
Fixes: 168b8c29cedb ("hw/riscv/virt: Add a switch to disable ACPI") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231220193436.25909-1-heinrich.schuchardt@canonical.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
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#
257cfaed |
| 20-Oct-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
docs/system/riscv: update 'virt' machine core limit
The 'virt' RISC-V machine does not have a 8 core limit. The current limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at this mom
docs/system/riscv: update 'virt' machine core limit
The 'virt' RISC-V machine does not have a 8 core limit. The current limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at this moment.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231020200247.334403-2-dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
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#
257cfaed |
| 20-Oct-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
docs/system/riscv: update 'virt' machine core limit
The 'virt' RISC-V machine does not have a 8 core limit. The current limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at this mom
docs/system/riscv: update 'virt' machine core limit
The 'virt' RISC-V machine does not have a 8 core limit. The current limit is set in include/hw/riscv/virt.h, VIRT_CPUS_MAX, set to 512 at this moment.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1945 Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231020200247.334403-2-dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4 |
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#
c0716c81 |
| 29-Jun-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/riscv/virt: Restrict ACLINT to TCG
The Advanced Core Local Interruptor (ACLINT) device can only be used with TCG. Check for TCG enabled instead of KVM being not. Only add the property when TCG is
hw/riscv/virt: Restrict ACLINT to TCG
The Advanced Core Local Interruptor (ACLINT) device can only be used with TCG. Check for TCG enabled instead of KVM being not. Only add the property when TCG is used.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230629121103.87733-3-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4 |
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#
c0716c81 |
| 29-Jun-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/riscv/virt: Restrict ACLINT to TCG
The Advanced Core Local Interruptor (ACLINT) device can only be used with TCG. Check for TCG enabled instead of KVM being not. Only add the property when TCG is
hw/riscv/virt: Restrict ACLINT to TCG
The Advanced Core Local Interruptor (ACLINT) device can only be used with TCG. Check for TCG enabled instead of KVM being not. Only add the property when TCG is used.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230629121103.87733-3-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
e158a652 |
| 01-Jun-2023 |
Sunil V L <sunilvl@ventanamicro.com> |
docs/system: riscv: Add pflash usage details
pflash devices can be used in virt machine for different purposes like for ROM code or S-mode FW payload. Add a section in the documentation on how to us
docs/system: riscv: Add pflash usage details
pflash devices can be used in virt machine for different purposes like for ROM code or S-mode FW payload. Add a section in the documentation on how to use pflash devices for different purposes.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230601045910.18646-4-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
e158a652 |
| 01-Jun-2023 |
Sunil V L <sunilvl@ventanamicro.com> |
docs/system: riscv: Add pflash usage details
pflash devices can be used in virt machine for different purposes like for ROM code or S-mode FW payload. Add a section in the documentation on how to us
docs/system: riscv: Add pflash usage details
pflash devices can be used in virt machine for different purposes like for ROM code or S-mode FW payload. Add a section in the documentation on how to use pflash devices for different purposes.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230601045910.18646-4-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0 |
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#
0c2d4671 |
| 05-Sep-2022 |
Alex Bennée <alex.bennee@linaro.org> |
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit in with the other examples on the page.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0 |
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#
0c2d4671 |
| 05-Sep-2022 |
Alex Bennée <alex.bennee@linaro.org> |
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit in with the other examples on the page.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0 |
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#
0c2d4671 |
| 05-Sep-2022 |
Alex Bennée <alex.bennee@linaro.org> |
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit in with the other examples on the page.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0 |
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#
0c2d4671 |
| 05-Sep-2022 |
Alex Bennée <alex.bennee@linaro.org> |
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit in with the other examples on the page.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0 |
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#
0c2d4671 |
| 05-Sep-2022 |
Alex Bennée <alex.bennee@linaro.org> |
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit in with the other examples on the page.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0 |
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#
0c2d4671 |
| 05-Sep-2022 |
Alex Bennée <alex.bennee@linaro.org> |
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit
docs/system: clean up code escape for riscv virt platform
The example code is rendered slightly mangled due to missing code block. Properly escape the code block and add shell prompt and qemu to fit in with the other examples on the page.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220905163939.1599368-1-alex.bennee@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
325b7c4e |
| 27-Apr-2022 |
Alistair Francis <alistair.francis@wdc.com> |
hw/riscv: Enable TPM backends
Imply the TPM sysbus devices. This allows users to add TPM devices to the RISC-V virt board.
This was tested by first creating an emulated TPM device:
swtpm socke
hw/riscv: Enable TPM backends
Imply the TPM sysbus devices. This allows users to add TPM devices to the RISC-V virt board.
This was tested by first creating an emulated TPM device:
swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \ --ctrl type=unixio,path=swtpm-sock
Then launching QEMU with:
-chardev socket,id=chrtpm,path=swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm \ -device tpm-tis-device,tpmdev=tpm0
The TPM device can be seen in the memory tree and the generated device tree.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0 |
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#
c65bc383 |
| 20-Feb-2022 |
Anup Patel <anup.patel@wdc.com> |
docs/system: riscv: Document AIA options for virt machine
We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options.
Signed-off-by
docs/system: riscv: Document AIA options for virt machine
We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220220085526.808674-5-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
7035b842 |
| 08-Feb-2022 |
Yu Li <liyu.yukiteru@bytedance.com> |
docs/system: riscv: Update description of CPU
Since the hypervisor extension been non experimental and enabled for default CPU, the previous command is no longer available and the option `x-h=true`
docs/system: riscv: Update description of CPU
Since the hypervisor extension been non experimental and enabled for default CPU, the previous command is no longer available and the option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1 |
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#
954886ea |
| 31-Aug-2021 |
Anup Patel <anup.patel@wdc.com> |
hw/riscv: virt: Add optional ACLINT support to virt machine
We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line.
hw/riscv: virt: Add optional ACLINT support to virt machine
We extend virt machine to emulate ACLINT devices only when "aclint=on" parameter is passed along with machine name in QEMU command-line.
Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20210831110603.338681-5-anup.patel@wdc.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1 |
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#
6df743dc |
| 26-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
docs: Format literals correctly
In rST markup, single backticks `like this` represent "interpreted text", which can be handled as a bunch of different things if tagged with a specific "role": https:
docs: Format literals correctly
In rST markup, single backticks `like this` represent "interpreted text", which can be handled as a bunch of different things if tagged with a specific "role": https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#interpreted-text (the most common one for us is "reference to a URL, which gets hyperlinked").
The default "role" if none is specified is "title_reference", intended for references to book or article titles, and it renders into the HTML as <cite>...</cite> (usually comes out as italics).
This commit fixes various places in the manual which were using single backticks when double backticks (for literal text) were intended, and covers those files where only one or two instances of these errors were made.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v6.1.0-rc0 |
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#
85198f18 |
| 27-Jun-2021 |
Bin Meng <bmeng.cn@gmail.com> |
docs/system: riscv: Add documentation for virt machine
This adds detailed documentation for RISC-V `virt` machine, including the following information:
- Supported devices - Hardware configurat
docs/system: riscv: Add documentation for virt machine
This adds detailed documentation for RISC-V `virt` machine, including the following information:
- Supported devices - Hardware configuration information - Boot options - Running Linux kernel - Running U-Boot
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210627142816.19789-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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