c4c12ee4 | 29-Mar-2024 |
Arnaud Minier <arnaud.minier@telecom-paris.fr> |
hw/char/stm32l4x5_usart: Add options for serial parameters setting
Add a function to change the settings of the serial connection.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Sign
hw/char/stm32l4x5_usart: Add options for serial parameters setting
Add a function to change the settings of the serial connection.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240329174402.60382-4-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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87b77e6e | 29-Mar-2024 |
Arnaud Minier <arnaud.minier@telecom-paris.fr> |
hw/char/stm32l4x5_usart: Enable serial read and write
Implement the ability to read and write characters to the usart using the serial port.
The character transmission is based on the cmsdk-apb-uar
hw/char/stm32l4x5_usart: Enable serial read and write
Implement the ability to read and write characters to the usart using the serial port.
The character transmission is based on the cmsdk-apb-uart implementation.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240329174402.60382-3-arnaud.minier@telecom-paris.fr [PMM: fixed a few checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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4fb37aea | 29-Mar-2024 |
Arnaud Minier <arnaud.minier@telecom-paris.fr> |
hw/char: Implement STM32L4x5 USART skeleton
Add the basic infrastructure (register read/write, type...) to implement the STM32L4x5 USART.
Also create different types for the USART, UART and LPUART
hw/char: Implement STM32L4x5 USART skeleton
Add the basic infrastructure (register read/write, type...) to implement the STM32L4x5 USART.
Also create different types for the USART, UART and LPUART of the STM32L4x5 to deduplicate code and enable the implementation of different behaviors depending on the type.
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240329174402.60382-2-arnaud.minier@telecom-paris.fr [PMM: update to new reset hold method signature; fixed a few checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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1d1afd9f | 14-Jan-2024 |
Bernhard Beschow <shentey@gmail.com> |
hw/char/parallel-isa: Implement relocation and enabling/disabling for TYPE_ISA_PARALLEL
The real SuperI/O chips emulated by QEMU allow for relocating and enabling or disabling their SuperI/O functio
hw/char/parallel-isa: Implement relocation and enabling/disabling for TYPE_ISA_PARALLEL
The real SuperI/O chips emulated by QEMU allow for relocating and enabling or disabling their SuperI/O functions via software. So far this is not implemented. Prepare for that by adding isa_parallel_set_{enabled,iobase}.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20240114123911.4877-10-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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7812dbc5 | 14-Jan-2024 |
Bernhard Beschow <shentey@gmail.com> |
hw/char/serial-isa: Implement relocation and enabling/disabling for TYPE_ISA_SERIAL
The real SuperI/O chips emulated by QEMU allow for relocating and enabling or disabling their SuperI/O functions v
hw/char/serial-isa: Implement relocation and enabling/disabling for TYPE_ISA_SERIAL
The real SuperI/O chips emulated by QEMU allow for relocating and enabling or disabling their SuperI/O functions via software. So far this is not implemented. Prepare for that by adding isa_serial_set_{enabled,iobase}.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20240114123911.4877-9-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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a72ccc7f | 16-Oct-2023 |
David Woodhouse <dwmw@amazon.co.uk> |
hw/xen: add support for Xen primary console in emulated mode
The primary console is special because the toolstack maps a page into the guest for its ring, and also allocates the guest-side event cha
hw/xen: add support for Xen primary console in emulated mode
The primary console is special because the toolstack maps a page into the guest for its ring, and also allocates the guest-side event channel. The guest's grant table is even primed to export that page using a known grant ref#. Add support for all that in emulated mode, so that we can have a primary console.
For reasons unclear, the backends running under real Xen don't just use a mapping of the well-known GNTTAB_RESERVED_CONSOLE grant ref (which would also be in the ring-ref node in XenStore). Instead, the toolstack sets the ring-ref node of the primary console to the GFN of the guest page. The backend is expected to handle that special case and map it with foreignmem operations instead.
We don't have an implementation of foreignmem ops for emulated Xen mode, so just make it map GNTTAB_RESERVED_CONSOLE instead. This would probably work for real Xen too, but we can't work out how to make real Xen create a primary console of type "ioemu" to make QEMU drive it, so we can't test that; might as well leave it as it is for now under Xen.
Now at last we can boot the Xen PV shim and run PV kernels in QEMU.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Paul Durrant <paul@xen.org>
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2e9cb201 | 30-Oct-2023 |
Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> |
hw/char/stm32f2xx_usart: Update IRQ when DR is written
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair F
hw/char/stm32f2xx_usart: Update IRQ when DR is written
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Message-id: 20231030151528.1138131-3-hans-erik.floryd@rt-labs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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058096f1 | 21-Jul-2023 |
Thomas Huth <thuth@redhat.com> |
hw/char/riscv_htif: Fix the console syscall on big endian hosts
Values that have been read via cpu_physical_memory_read() from the guest's memory have to be swapped in case the host endianess differ
hw/char/riscv_htif: Fix the console syscall on big endian hosts
Values that have been read via cpu_physical_memory_read() from the guest's memory have to be swapped in case the host endianess differs from the guest.
Fixes: a6e13e31d5 ("riscv_htif: Support console output via proxy syscall") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230721094720.902454-3-thuth@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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07738852 | 22-May-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/char/pl011: Replace magic values by register field definitions
0x400 is Data Register Break Error (DR_BE), 0x10 is Line Control Register Fifo Enabled (LCR_FEN) and 0x1 is Send Break (LCR_BRK).
S
hw/char/pl011: Replace magic values by register field definitions
0x400 is Data Register Break Error (DR_BE), 0x10 is Line Control Register Fifo Enabled (LCR_FEN) and 0x1 is Send Break (LCR_BRK).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230522153144.30610-7-philmd@linaro.org>
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