#
d09923ad |
| 06-Jan-2024 |
Samuel Tardieu <sam@rfc1149.net> |
hw/intc/armv7m_nvic: add "num-prio-bits" property
Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up m
hw/intc/armv7m_nvic: add "num-prio-bits" property
Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up must use 3 or more bits.
This adds a "num-prio-bits" property which will get sensible default values if unset (2 or 8 depending on the device). Unless a SOC specifies the number of bits to use, the previous behavior is maintained for backward compatibility.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240106181503.1746200-2-sam@rfc1149.net Suggested-by: Anton Kochkov <anton.kochkov@proton.me> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d09923ad |
| 06-Jan-2024 |
Samuel Tardieu <sam@rfc1149.net> |
hw/intc/armv7m_nvic: add "num-prio-bits" property
Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up m
hw/intc/armv7m_nvic: add "num-prio-bits" property
Cortex-M NVIC can have a different number of priority bits. Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based on ARMv7m and up must use 3 or more bits.
This adds a "num-prio-bits" property which will get sensible default values if unset (2 or 8 depending on the device). Unless a SOC specifies the number of bits to use, the previous behavior is maintained for backward compatibility.
Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240106181503.1746200-2-sam@rfc1149.net Suggested-by: Anton Kochkov <anton.kochkov@proton.me> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.4, v7.2.8 |
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#
45b1f81d |
| 21-Dec-2023 |
Richard Henderson <richard.henderson@linaro.org> |
hw/intc: Constify VMState
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-35-richard.henderson@linaro.org>
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
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#
5a534314 |
| 24-Oct-2023 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
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#
5a534314 |
| 24-Oct-2023 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0 |
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#
673d8215 |
| 14-Jul-2023 |
Michael Tokarev <mjt@tls.msk.ru> |
arm: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0 |
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#
673d8215 |
| 14-Jul-2023 |
Michael Tokarev <mjt@tls.msk.ru> |
arm: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0 |
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#
673d8215 |
| 14-Jul-2023 |
Michael Tokarev <mjt@tls.msk.ru> |
arm: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
d4fb55a6 |
| 20-Feb-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/intc/armv7m_nvic: Use QOM cast CPU() macro
Avoid accessing 'parent_obj' directly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Mess
hw/intc/armv7m_nvic: Use QOM cast CPU() macro
Avoid accessing 'parent_obj' directly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230220115114.25237-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
2b77ad4d |
| 17-Feb-2023 |
Fabiano Rosas <farosas@suse.de> |
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
This is in preparation to moving the hflags code into its own file under the tcg/ directory.
Signed-off-by: Fabiano Rosas <farosas@suse.de
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
This is in preparation to moving the hflags code into its own file under the tcg/ directory.
Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
8f4e07c9 |
| 06-Feb-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathie
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
8f4e07c9 |
| 06-Feb-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathie
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
8f4e07c9 |
| 06-Feb-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathie
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
8f4e07c9 |
| 06-Feb-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathie
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
8f4e07c9 |
| 06-Feb-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathie
target/arm: Store CPUARMState::nvic as NVICState*
There is no point in using a void pointer to access the NVIC. Use the real type to avoid casting it while debugging.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230206223502.25122-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
9d5a9ae9 |
| 28-Jun-2022 |
Peter Maydell <peter.maydell@linaro.org> |
hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
In the M-profile Arm ARM, rule R_CVJS defines when an interrupt should be set to the Pending state: A) when the input line
hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
In the M-profile Arm ARM, rule R_CVJS defines when an interrupt should be set to the Pending state: A) when the input line is high and the interrupt is not Active B) when the input line transitions from low to high and the interrupt is Active (Note that the first of these is an ongoing condition, and the second is a point-in-time event.)
This can be rephrased as: 1 when the line goes from low to high, set Pending 2 when Active goes from 1 to 0, if line is high then set Pending 3 ignore attempts to clear Pending when the line is high and Active is 0
where 1 covers both B and one of the "transition into condition A" cases, 2 deals with the other "transition into condition A" possibility, and 3 is "don't drop Pending if we're already in condition A". Transitions out of condition A don't affect Pending state.
We handle case 1 in set_irq_level(). For an interrupt (as opposed to other kinds of exception) the only place where we clear Active is in armv7m_nvic_complete_irq(), where we handle case 2 by checking for whether we need to re-pend the exception. For case 3, the only places where we clear Pending state on an interrupt are in armv7m_nvic_acknowledge_irq() (where we are setting Active so it doesn't count) and for writes to NVIC_ICPRn.
It is the "write to NVIC_ICPRn" case that we missed: we must ignore this if the input line is high and the interrupt is not Active. (This required behaviour is differently and perhaps more clearly stated in the v7M Arm ARM, which has pseudocode in section B3.4.1 that implies it.)
Reported-by: Igor Kotrasiński <i.kotrasinsk@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220628154724.3297442-1-peter.maydell@linaro.org
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Revision tags: v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0, v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1, v6.1.0, v6.1.0-rc4 |
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#
2089c010 |
| 12-Aug-2021 |
Peter Maydell <peter.maydell@linaro.org> |
arm: Move system PPB container handling to armv7m
Instead of having the NVIC device provide a single sysbus memory region covering the whole of the "System PPB" space, which implements the default b
arm: Move system PPB container handling to armv7m
Instead of having the NVIC device provide a single sysbus memory region covering the whole of the "System PPB" space, which implements the default behaviour for unimplemented ranges and provides the NS alias window to the sysregs as well as the main sysreg MR, move this handling to the container armv7m device. The NVIC now provides a single memory region which just implements the system registers. This consolidates all the handling of "map various devices in the PPB" into the armv7m container where it belongs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-4-peter.maydell@linaro.org
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#
e36a25cb |
| 12-Aug-2021 |
Peter Maydell <peter.maydell@linaro.org> |
arm: Move systick device creation from NVIC to ARMv7M object
There's no particular reason why the NVIC should be owning the SysTick device objects; move them into the ARMv7M container object instead
arm: Move systick device creation from NVIC to ARMv7M object
There's no particular reason why the NVIC should be owning the SysTick device objects; move them into the ARMv7M container object instead, as part of consolidating the "create the devices which are built into an M-profile CPU and map them into their architected locations in the address space" work into one place.
This involves temporarily creating a duplicate copy of the nvic_sysreg_ns_ops struct and its read/write functions (renamed as v7m_sysreg_ns_*), but we will delete the NVIC's copy of this code in a subsequent patch.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20210812093356.1946-3-peter.maydell@linaro.org
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#
2f9db77e |
| 12-Aug-2021 |
Peter Maydell <peter.maydell@linaro.org> |
arm: Move M-profile RAS register block into its own device
Currently we implement the RAS register block within the NVIC device. It isn't really very tightly coupled with the NVIC proper, so instead
arm: Move M-profile RAS register block into its own device
Currently we implement the RAS register block within the NVIC device. It isn't really very tightly coupled with the NVIC proper, so instead move it out into a sysbus device of its own and have the top level ARMv7M container create it and map it into memory at the right address.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-2-peter.maydell@linaro.org
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Revision tags: v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1 |
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#
845d27a9 |
| 23-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if the register is accessed NonSecure and the highest priority
hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if the register is accessed NonSecure and the highest priority pending enabled exception (that would be returned in the VECTPENDING field) targets Secure, then the VECTPENDING field must read 1 rather than the exception number of the pending exception. Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210723162146.5167-7-peter.maydell@linaro.org
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#
7caad657 |
| 23-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of the register. We were incorrectly masking it to 8 bits, so it would report
hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
The VECTPENDING field in the ICSR is 9 bits wide, in bits [20:12] of the register. We were incorrectly masking it to 8 bits, so it would report the wrong value if the pending exception was greater than 256. Fix the bug.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210723162146.5167-6-peter.maydell@linaro.org
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#
41487794 |
| 23-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
The ISCR.ISRPENDING bit is set when an external interrupt is pending. This is true whether that external interrupt is e
hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
The ISCR.ISRPENDING bit is set when an external interrupt is pending. This is true whether that external interrupt is enabled or not. This means that we can't use 's->vectpending == 0' as a shortcut to "ISRPENDING is zero", because s->vectpending indicates only the highest priority pending enabled interrupt.
Remove the incorrect optimization so that if there is no pending enabled interrupt we fall through to scanning through the whole interrupt array.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210723162146.5167-5-peter.maydell@linaro.org
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Revision tags: v6.1.0-rc0 |
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#
a25c84c7 |
| 14-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
hw/intc/armv7m_nvic: Remove stale comment
In commit da6d674e509f0939b we split the NVIC code out from the GIC. This allowed us to specify the NVIC's default value for the num-irq property (64) in th
hw/intc/armv7m_nvic: Remove stale comment
In commit da6d674e509f0939b we split the NVIC code out from the GIC. This allowed us to specify the NVIC's default value for the num-irq property (64) in the usual way in its property list, and we deleted the previous hack where we updated the value in the state struct in the instance init function. Remove a stale comment about that hack which we forgot to delete at that time.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210614161243.14211-1-peter.maydell@linaro.org
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Revision tags: v6.0.0, v6.0.0-rc5, v6.0.0-rc4 |
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#
2068cabd |
| 16-Apr-2021 |
Thomas Huth <thuth@redhat.com> |
Do not include cpu.h if it's not really necessary
Stop including cpu.h in files that don't need it.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-4-thuth@redhat.
Do not include cpu.h if it's not really necessary
Stop including cpu.h in files that don't need it.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-4-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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Revision tags: v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0 |
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#
5b7d6370 |
| 10-Dec-2020 |
Peter Maydell <peter.maydell@linaro.org> |
hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN
The CCR is a register most of whose bits are banked between security states but where BFHFNMIGN is not, and we keep it in the non-secure entry
hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGN
The CCR is a register most of whose bits are banked between security states but where BFHFNMIGN is not, and we keep it in the non-secure entry of the v7m.ccr[] array. The logic which tries to handle this bit fails to implement the "RAZ/WI from Nonsecure if AIRCR.BFHFNMINS is zero" requirement; correct the omission.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201210201433.26262-2-peter.maydell@linaro.org
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