2fdc20f9 | 29-Jan-2024 |
Paolo Bonzini <pbonzini@redhat.com> |
smc37c669: remove useless is_enabled functions
Calls to is_enabled are bounded to indices that actually exist in the SuperIO device. Therefore, the is_enabled functions in smc37c669 are not doing a
smc37c669: remove useless is_enabled functions
Calls to is_enabled are bounded to indices that actually exist in the SuperIO device. Therefore, the is_enabled functions in smc37c669 are not doing anything and they can be removed.
Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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fbd75800 | 13-Feb-2024 |
Paolo Bonzini <pbonzini@redhat.com> |
hw/isa: extract FDC37M81X to a separate file
isa-superio.c currently defines a SuperIO chip that is not used by any other user of the file. Extract the chip to a separate file.
Reviewed-by: Bernha
hw/isa: extract FDC37M81X to a separate file
isa-superio.c currently defines a SuperIO chip that is not used by any other user of the file. Extract the chip to a separate file.
Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20240213155005.109954-7-pbonzini@redhat.com> [PMD: Update MAINTAINERS] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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413d0ccb | 13-Feb-2024 |
Paolo Bonzini <pbonzini@redhat.com> |
hw/isa: specify instance_size in isa_superio_type_info
Right now all subclasses of TYPE_ISA_SUPERIO have to specify an instance_size, because the ISASuperIODevice struct adds fields to ISADevice but
hw/isa: specify instance_size in isa_superio_type_info
Right now all subclasses of TYPE_ISA_SUPERIO have to specify an instance_size, because the ISASuperIODevice struct adds fields to ISADevice but the type does not include the increased instance size. Failure to do so results in an access past the bounds of struct ISADevice as soon as isa_superio_realize is called. Fix this by specifying the instance_size already in the superclass.
Fixes: 4c3119a6e3 ("hw/isa/superio: Factor out the parallel code from pc87312.c") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20240213155005.109954-6-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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cf5f5f92 | 13-Feb-2024 |
Paolo Bonzini <pbonzini@redhat.com> |
hw/isa: fix ISA_SUPERIO dependencies
ISA_SUPERIO does not provide an ISA bus, so it should not select the symbol: instead it requires one. Among its users, VT82C686 is the only one that is a PCI-IS
hw/isa: fix ISA_SUPERIO dependencies
ISA_SUPERIO does not provide an ISA bus, so it should not select the symbol: instead it requires one. Among its users, VT82C686 is the only one that is a PCI-ISA bridge and does not already select ISA_BUS.
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20240213155005.109954-5-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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f669bd89 | 01-Feb-2024 |
Zhao Liu <zhao1.liu@intel.com> |
hw/isa/pc87312: Consolidate the use of device_class_set_parent_realize()
Use device_class_set_parent_realize() to set parent realize() directly.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Review
hw/isa/pc87312: Consolidate the use of device_class_set_parent_realize()
Use device_class_set_parent_realize() to set parent realize() directly.
Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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0ed083a1 | 26-Nov-2023 |
BALATON Zoltan <balaton@eik.bme.hu> |
hw/audio/via-ac97: Route interrupts using via_isa_set_irq()
This device is a function of VIA south bridge and should allow setting interrupt routing within that chip. This is implemented in via_isa_
hw/audio/via-ac97: Route interrupts using via_isa_set_irq()
This device is a function of VIA south bridge and should allow setting interrupt routing within that chip. This is implemented in via_isa_set_irq().
Fixes: eb604411a78b82c468e2b8d81a9401eb8b9c7658 Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <5329840e4be6dd8ae143d07cbfe61d8d2d106654.1701035944.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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01f13ee2 | 26-Nov-2023 |
BALATON Zoltan <balaton@eik.bme.hu> |
hw/isa/vt82c686: Route PIRQ inputs using via_isa_set_irq()
The chip has 4 pins (called PIRQA-D in VT82C686B and PINTA-D in VT8231) that are meant to be connected to PCI IRQ lines and allow routing P
hw/isa/vt82c686: Route PIRQ inputs using via_isa_set_irq()
The chip has 4 pins (called PIRQA-D in VT82C686B and PINTA-D in VT8231) that are meant to be connected to PCI IRQ lines and allow routing PCI interrupts to the ISA PIC. Route these in via_isa_set_irq() to make it possible to share them with internal functions that can also be routed to the same ISA IRQs.
Fixes: 2fdadd02e675caca4aba4ae26317701fe2c4c901 Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-ID: <8c4513d8b78fac40e6d4e65a0a4b3a7f2f278a4b.1701035944.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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12cecd45 | 07-Oct-2023 |
Bernhard Beschow <shentey@gmail.com> |
hw/isa/piix: Implement multi-process QEMU support also for PIIX4
So far multi-process QEMU was only implemented for PIIX3. Move the support into the base class to achieve feature parity between both
hw/isa/piix: Implement multi-process QEMU support also for PIIX4
So far multi-process QEMU was only implemented for PIIX3. Move the support into the base class to achieve feature parity between both device models.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20231007123843.127151-29-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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a203cc53 | 07-Oct-2023 |
Bernhard Beschow <shentey@gmail.com> |
hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
Now that both PIIX3 and PIIX4 use piix_set_irq() to trigger PCI IRQs the wiring in the respective realize methods can be shared, to
hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring
Now that both PIIX3 and PIIX4 use piix_set_irq() to trigger PCI IRQs the wiring in the respective realize methods can be shared, too.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-28-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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0c9fd5a3 | 07-Oct-2023 |
Bernhard Beschow <shentey@gmail.com> |
hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible with Xen which relies on pci_bus_fire_intx_routing_notifier() to
hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4
Speeds up PIIX4 which resolves an old TODO. Also makes PIIX4 compatible with Xen which relies on pci_bus_fire_intx_routing_notifier() to be fired.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-27-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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2a62c479 | 07-Oct-2023 |
Bernhard Beschow <shentey@gmail.com> |
hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
PIIX4 will get the same optimizations which are already implemented for PIIX3.
Signed-off-by: Bernhard Beschow <shentey@gmail
hw/isa/piix: Rename functions to be shared for PCI interrupt triggering
PIIX4 will get the same optimizations which are already implemented for PIIX3.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-26-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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2922dbc2 | 07-Oct-2023 |
Bernhard Beschow <shentey@gmail.com> |
hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
Resolves duplicate code. Also makes PIIX4 respect the PIIX3 properties which get added, too. This allows for using PIIX4 in the PC machin
hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4
Resolves duplicate code. Also makes PIIX4 respect the PIIX3 properties which get added, too. This allows for using PIIX4 in the PC machine.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20231007123843.127151-25-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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7d6f2659 | 07-Oct-2023 |
Bernhard Beschow <shentey@gmail.com> |
hw/isa/piix: Share PIIX3's base class with PIIX4
Having a common base class will allow for futher code sharing between PIIX3 and PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface.
hw/isa/piix: Share PIIX3's base class with PIIX4
Having a common base class will allow for futher code sharing between PIIX3 and PIIX4. Moreover, it makes PIIX4 implement the acpi-dev-aml-interface.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-24-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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f97479ca | 07-Oct-2023 |
Bernhard Beschow <shentey@gmail.com> |
hw/isa/piix: Harmonize names of reset control memory regions
There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4.
Signed-
hw/isa/piix: Harmonize names of reset control memory regions
There is no need for having different names here. Having the same name further allows code to be shared between PIIX3 and PIIX4.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231007123843.127151-23-shentey@gmail.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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