1a909e3d | 28-Feb-2024 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
hw/pci: Always call pcie_sriov_pf_reset()
Call pcie_sriov_pf_reset() from pci_do_device_reset() just as we do for msi_reset() and msix_reset() to prevent duplicating code for each SR-IOV PF.
Signed
hw/pci: Always call pcie_sriov_pf_reset()
Call pcie_sriov_pf_reset() from pci_do_device_reset() just as we do for msi_reset() and msix_reset() to prevent duplicating code for each SR-IOV PF.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240228-reuse-v8-5-282660281e60@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>
show more ...
|
c8bc4db4 | 28-Feb-2024 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
pcie_sriov: Reset SR-IOV extended capability
pcie_sriov_pf_disable_vfs() is called when resetting the PF, but it only disables VFs and does not reset SR-IOV extended capability, leaking the state an
pcie_sriov: Reset SR-IOV extended capability
pcie_sriov_pf_disable_vfs() is called when resetting the PF, but it only disables VFs and does not reset SR-IOV extended capability, leaking the state and making the VF Enable register inconsistent with the actual state.
Replace pcie_sriov_pf_disable_vfs() with pcie_sriov_pf_reset(), which does not only disable VFs but also resets the capability.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240228-reuse-v8-3-282660281e60@daynix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>
show more ...
|
fa905f65 | 10-Mar-2024 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: add machine compatibility parameter to enable msix exclusive bar
Commit 1901b4967c3f ("hw/block/nvme: move msix table and pba to BAR 0") moved the MSI-X table and PBA to BAR 0 to make room
hw/nvme: add machine compatibility parameter to enable msix exclusive bar
Commit 1901b4967c3f ("hw/block/nvme: move msix table and pba to BAR 0") moved the MSI-X table and PBA to BAR 0 to make room for enabling CMR and PMR at the same time. As reported by Julien Grall in #2184, this breaks migration through system hibernation.
Add a machine compatibility parameter and set it on machines pre 6.0 to enable the old behavior automatically, restoring the hibernation migration support.
Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2184 Fixes: 1901b4967c3f ("hw/block/nvme: move msix table and pba to BAR 0") Reported-by: Julien Grall julien@xen.org Tested-by: Julien Grall julien@xen.org Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
show more ...
|
ee7bda4d | 10-Mar-2024 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: generalize the mbar size helper
Generalize the mbar size helper such that it can handle cases where the MSI-X table and PBA are expected to be in an exclusive bar.
Cc: qemu-stable@nongnu.o
hw/nvme: generalize the mbar size helper
Generalize the mbar size helper such that it can handle cases where the MSI-X table and PBA are expected to be in an exclusive bar.
Cc: qemu-stable@nongnu.org Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
show more ...
|
bdc31646 | 22-Feb-2024 |
Roque Arcudia Hernandez <roqueh@google.com> |
hw/nvme: Add NVMe NGUID property
This patch adds a way to specify an NGUID for a given NVMe Namespace using a string of hexadecimal digits with an optional '-' separator to group bytes. For instance
hw/nvme: Add NVMe NGUID property
This patch adds a way to specify an NGUID for a given NVMe Namespace using a string of hexadecimal digits with an optional '-' separator to group bytes. For instance:
-device nvme-ns,nguid="e9accd3b83904e13167cf0593437f57d"
If provided, the NGUID will be part of the Namespace Identification Descriptor list and the Identify Namespace data.
Signed-off-by: Roque Arcudia Hernandez <roqueh@google.com> Signed-off-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
show more ...
|
8c78015a | 08-Feb-2024 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: fix invalid check on mcl
The number of logical blocks within a source range is converted into a 1s based number at the time of parsing. However, when verifying the copy length we add one ag
hw/nvme: fix invalid check on mcl
The number of logical blocks within a source range is converted into a 1s based number at the time of parsing. However, when verifying the copy length we add one again, causing the check against MCL to fail in error.
Cc: qemu-stable@nongnu.org Fixes: 381ab99d8587 ("hw/nvme: check maximum copy length (MCL) for COPY") Reviewed-by: Minwoo Im <minwoo.im@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
show more ...
|
b3c82467 | 11-Aug-2023 |
Peter Maydell <peter.maydell@linaro.org> |
hw/nvme: Avoid dynamic stack allocation
Instead of using a variable-length array in nvme_map_prp(), allocate on the stack with a g_autofree pointer.
The codebase has very few VLAs, and if we can ge
hw/nvme: Avoid dynamic stack allocation
Instead of using a variable-length array in nvme_map_prp(), allocate on the stack with a g_autofree pointer.
The codebase has very few VLAs, and if we can get rid of them all we can make the compiler error on new additions. This is a defensive measure against security bugs where an on-stack dynamic allocation isn't correctly size-checked (e.g. CVE-2021-3527).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
show more ...
|
3439ba9c | 08-Aug-2023 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: fix null pointer access in ruh update
The Reclaim Unit Update operation in I/O Management Receive does not verify the presence of a configured endurance group prior to accessing it.
Fix th
hw/nvme: fix null pointer access in ruh update
The Reclaim Unit Update operation in I/O Management Receive does not verify the presence of a configured endurance group prior to accessing it.
Fix this.
Cc: qemu-stable@nongnu.org Fixes: 73064edfb864 ("hw/nvme: flexible data placement emulation") Reviewed-by: Jesper Wendel Devantier <j.devantier@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
show more ...
|
6a33f2e9 | 19-Jul-2023 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: fix compliance issue wrt. iosqes/iocqes
As of prior to this patch, the controller checks the value of CC.IOCQES and CC.IOSQES prior to enabling the controller. As reported by Ben in GitLab
hw/nvme: fix compliance issue wrt. iosqes/iocqes
As of prior to this patch, the controller checks the value of CC.IOCQES and CC.IOSQES prior to enabling the controller. As reported by Ben in GitLab issue #1691, this is not spec compliant. The controller should only check these values when queues are created.
This patch moves these checks to nvme_create_cq(). We do not need to check it in nvme_create_sq() since that will error out if the completion queue is not already created.
Also, since the controller exclusively supports SQEs of size 64 bytes and CQEs of size 16 bytes, hard code that.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1691 Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
show more ...
|
ce801773 | 14-Feb-2023 |
Klaus Jensen <k.jensen@samsung.com> |
hw/nvme: add placement handle list ranges
Allow the placement handles to be specified as ranges, i.e. `fdp.ruhs=1:3-5` will attempt to assign ruh 1, 3, 4 and 5 to the namespace.
Reviewed-by: Jesper
hw/nvme: add placement handle list ranges
Allow the placement handles to be specified as ranges, i.e. `fdp.ruhs=1:3-5` will attempt to assign ruh 1, 3, 4 and 5 to the namespace.
Reviewed-by: Jesper Wendel Devantier <j.devantier@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
show more ...
|