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fcc63904 |
| 16-Oct-2023 |
Saif Abrar <saif.abrar@linux.vnet.ibm.com> |
hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5. Apply bit-masks within xscom-write methods. Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abr
hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5. Apply bit-masks within xscom-write methods. Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20231016175948.10869-1-saif.abrar@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
fcc63904 |
| 16-Oct-2023 |
Saif Abrar <saif.abrar@linux.vnet.ibm.com> |
hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5. Apply bit-masks within xscom-write methods. Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abr
hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5. Apply bit-masks within xscom-write methods. Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20231016175948.10869-1-saif.abrar@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
fcc63904 |
| 16-Oct-2023 |
Saif Abrar <saif.abrar@linux.vnet.ibm.com> |
hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5. Apply bit-masks within xscom-write methods. Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abr
hw/pci-host: Update PHB5 XSCOM registers
Add new XSCOM registers introduced in PHB5. Apply bit-masks within xscom-write methods. Bit-masks specified using PPC_BITMASK macro.
Signed-off-by: Saif Abrar <saif.abrar@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-ID: <20231016175948.10869-1-saif.abrar@linux.vnet.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0, v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0 |
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#
34b0696b |
| 02-Mar-2022 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: Add support for PHB5 "Address-based trigger" mode
When the Address-Based Interrupt Trigger mode is activated, the PHB maps the interrupt source number into the interrupt command address. Th
ppc/pnv: Add support for PHB5 "Address-based trigger" mode
When the Address-Based Interrupt Trigger mode is activated, the PHB maps the interrupt source number into the interrupt command address. The PHB directly triggers the IC ESB page of the interrupt number and not the notify page of the IC anymore.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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c6b8cc37 |
| 02-Mar-2022 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: Add support for PQ offload on PHB5
The PQ_disable configuration bit disables the check done on the PQ state bits when processing new MSI interrupts. When bit 9 is enabled, the PHB forwards
ppc/pnv: Add support for PQ offload on PHB5
The PQ_disable configuration bit disables the check done on the PQ state bits when processing new MSI interrupts. When bit 9 is enabled, the PHB forwards any MSI trigger to the XIVE interrupt controller without checking the PQ state bits. The XIVE IC knows from the trigger message that the PQ bits have not been checked and performs the check locally.
This configuration bit only applies to MSIs and LSIs are still checked on the PHB to handle the assertion level.
PQ_disable enablement is a requirement for StoreEOI.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1, v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0, v6.0.0, v6.0.0-rc5, v6.0.0-rc4, v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0, v5.2.0, v5.2.0-rc4, v5.2.0-rc3, v5.2.0-rc2, v5.2.0-rc1, v5.2.0-rc0, v5.0.1, v5.1.0, v5.1.0-rc3, v5.1.0-rc2, v5.1.0-rc1, v5.1.0-rc0, v4.2.1, v5.0.0, v5.0.0-rc4, v5.0.0-rc3, v5.0.0-rc2, v5.0.0-rc1, v5.0.0-rc0 |
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#
4f9924c4 |
| 27-Jan-2020 |
Benjamin Herrenschmidt <benh@kernel.crashing.org> |
ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
These changes introduces models for the PCIe Host Bridge (PHB4) of the POWER9 processor. It includes the PowerBus logic interface (PBCQ), IOMMU s
ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge
These changes introduces models for the PCIe Host Bridge (PHB4) of the POWER9 processor. It includes the PowerBus logic interface (PBCQ), IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI and LSI interrupt sources as found on a POWER9 system using the XIVE interrupt controller.
POWER9 processor comes with 3 PHB4 PEC (PCI Express Controller) and each PEC can have several PHBs. By default,
* PEC0 provides 1 PHB (PHB0) * PEC1 provides 2 PHBs (PHB1 and PHB2) * PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Each PEC has a set "global" registers and some "per-stack" (per-PHB) registers. Those are organized in two XSCOM ranges, the "Nest" range and the "PCI" range, each range contains both some "PEC" registers and some "per-stack" registers.
No default device layout is provided and PCI devices can be added on any of the available PCIe Root Port (pcie.0 .. 2 of a Power9 chip) with address 0x0 as the firwware (skiboot) only accepts a single device per root port. To run a simple system with a network and a storage adapters, use a command line options such as :
-device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0 -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0
-device megasas,id=scsi0,bus=pcie.1,addr=0x0 -drive file=$disk,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2
If more are needed, include a bridge.
Multi chip is supported, each chip adding its set of PHB4 controllers and its PCI busses. The model doesn't emulate the EEH error handling.
This model is not ready for hotplug yet.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [ clg: - numerous cleanups - commit log - fix for broken LSI support - PHB pic printinfo - large QOM rework ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200127144506.11132-2-clg@kaod.org> [dwg: Use device_class_set_props()] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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