Revision tags: v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10 |
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#
ee1004bb |
| 29-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
bulk: Access existing variables initialized to &S->F when available
When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also he
bulk: Access existing variables initialized to &S->F when available
When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also helps static analyzers.
Mechanical change using the following Coccinelle spatch script:
@@ type S, F; identifier s, m, v; @@ S *s; ... F *v = &s->m; <+... - &s->m + v ...+>
Inspired-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240129164514.73104-2-philmd@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> [thuth: Dropped hunks that need a rebase, and fixed sizeof() in pmu_realize()] Signed-off-by: Thomas Huth <thuth@redhat.com>
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Revision tags: v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10 |
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#
ee1004bb |
| 29-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
bulk: Access existing variables initialized to &S->F when available
When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also he
bulk: Access existing variables initialized to &S->F when available
When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also helps static analyzers.
Mechanical change using the following Coccinelle spatch script:
@@ type S, F; identifier s, m, v; @@ S *s; ... F *v = &s->m; <+... - &s->m + v ...+>
Inspired-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240129164514.73104-2-philmd@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> [thuth: Dropped hunks that need a rebase, and fixed sizeof() in pmu_realize()] Signed-off-by: Thomas Huth <thuth@redhat.com>
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Revision tags: v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10 |
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#
ee1004bb |
| 29-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
bulk: Access existing variables initialized to &S->F when available
When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also he
bulk: Access existing variables initialized to &S->F when available
When a variable is initialized to &struct->field, use it in place. Rationale: while this makes the code more concise, this also helps static analyzers.
Mechanical change using the following Coccinelle spatch script:
@@ type S, F; identifier s, m, v; @@ S *s; ... F *v = &s->m; <+... - &s->m + v ...+>
Inspired-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240129164514.73104-2-philmd@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com> [thuth: Dropped hunks that need a rebase, and fixed sizeof() in pmu_realize()] Signed-off-by: Thomas Huth <thuth@redhat.com>
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Revision tags: v8.2.1, v8.1.5, v7.2.9 |
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f4f318b4 |
| 18-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Move GTimer definitions to new 'gtimer.h' header
Move Arm A-class Generic Timer definitions to the new "target/arm/gtimer.h" header so units in hw/ which don't need access to ARMCPU inte
target/arm: Move GTimer definitions to new 'gtimer.h' header
Move Arm A-class Generic Timer definitions to the new "target/arm/gtimer.h" header so units in hw/ which don't need access to ARMCPU internals can use them without having to include the huge "cpu.h".
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-20-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.2.1, v8.1.5, v7.2.9 |
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f4f318b4 |
| 18-Jan-2024 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/arm: Move GTimer definitions to new 'gtimer.h' header
Move Arm A-class Generic Timer definitions to the new "target/arm/gtimer.h" header so units in hw/ which don't need access to ARMCPU inte
target/arm: Move GTimer definitions to new 'gtimer.h' header
Move Arm A-class Generic Timer definitions to the new "target/arm/gtimer.h" header so units in hw/ which don't need access to ARMCPU internals can use them without having to include the huge "cpu.h".
Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240118200643.29037-20-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v8.1.4, v7.2.8 |
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e3fe0bc6 |
| 21-Dec-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Constify VMState in machine.c
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.hend
target/arm: Constify VMState in machine.c
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-3-richard.henderson@linaro.org>
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
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5a534314 |
| 24-Oct-2023 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
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Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
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#
5a534314 |
| 24-Oct-2023 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
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Revision tags: v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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2b77ad4d |
| 17-Feb-2023 |
Fabiano Rosas <farosas@suse.de> |
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
This is in preparation to moving the hflags code into its own file under the tcg/ directory.
Signed-off-by: Fabiano Rosas <farosas@suse.de
target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled
This is in preparation to moving the hflags code into its own file under the tcg/ directory.
Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
fa05d1ab |
| 17-Feb-2023 |
Fabiano Rosas <farosas@suse.de> |
target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
This is in preparation for restricting compilation of some parts of debug_helper.c to TCG only.
Signed-off-by: Fabiano Rosas <farosas
target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled
This is in preparation for restricting compilation of some parts of debug_helper.c to TCG only.
Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
501e6d1f |
| 13-Feb-2023 |
Fabiano Rosas <farosas@suse.de> |
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
501e6d1f |
| 13-Feb-2023 |
Fabiano Rosas <farosas@suse.de> |
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
501e6d1f |
| 13-Feb-2023 |
Fabiano Rosas <farosas@suse.de> |
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
501e6d1f |
| 13-Feb-2023 |
Fabiano Rosas <farosas@suse.de> |
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
501e6d1f |
| 13-Feb-2023 |
Fabiano Rosas <farosas@suse.de> |
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
target/arm: Move PC alignment check
Move this earlier to make the next patch diff cleaner. While here update the comment slightly to not give the impression that the misalignment affects only TCG.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Fabiano Rosas <farosas@suse.de> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.2.0, v7.2.0-rc4 |
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#
761c4642 |
| 06-Dec-2022 |
Tobias Röhmel <tobias.roehmel@rwth-aachen.de> |
target/arm: Add PMSAv8r registers
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.m
target/arm: Add PMSAv8r registers
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.2.0, v7.2.0-rc4 |
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761c4642 |
| 06-Dec-2022 |
Tobias Röhmel <tobias.roehmel@rwth-aachen.de> |
target/arm: Add PMSAv8r registers
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.m
target/arm: Add PMSAv8r registers
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.2.0, v7.2.0-rc4 |
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#
761c4642 |
| 06-Dec-2022 |
Tobias Röhmel <tobias.roehmel@rwth-aachen.de> |
target/arm: Add PMSAv8r registers
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.m
target/arm: Add PMSAv8r registers
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> Message-id: 20221206102504.165775-6-tobias.roehmel@rwth-aachen.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
dc993a01 |
| 20-Jun-2022 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Add the SME ZA storage to CPUARMState
Place this late in the resettable section of the structure, to keep the most common element offsets from being > 64k.
Reviewed-by: Peter Maydell <p
target/arm: Add the SME ZA storage to CPUARMState
Place this late in the resettable section of the structure, to keep the most common element offsets from being > 64k.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-10-richard.henderson@linaro.org [PMM: expanded comment on zarray[] format] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
dc993a01 |
| 20-Jun-2022 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Add the SME ZA storage to CPUARMState
Place this late in the resettable section of the structure, to keep the most common element offsets from being > 64k.
Reviewed-by: Peter Maydell <p
target/arm: Add the SME ZA storage to CPUARMState
Place this late in the resettable section of the structure, to keep the most common element offsets from being > 64k.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-10-richard.henderson@linaro.org [PMM: expanded comment on zarray[] format] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d385a605 |
| 01-May-2022 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Avoid bare abort() or assert(0)
Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report.
Signed-off-by: Richard Henderson
target/arm: Avoid bare abort() or assert(0)
Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
d385a605 |
| 01-May-2022 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Avoid bare abort() or assert(0)
Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report.
Signed-off-by: Richard Henderson
target/arm: Avoid bare abort() or assert(0)
Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220501055028.646596-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0, v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0 |
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#
7055fe4b |
| 03-Nov-2021 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Assert thumb pc is aligned
Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere.
Expand a comment about aligning
target/arm: Assert thumb pc is aligned
Misaligned thumb PC is architecturally impossible. Assert is better than proceeding, in case we've missed something somewhere.
Expand a comment about aligning the pc in gdbstub. Fail an incoming migrate if a thumb pc is misaligned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v6.0.1 |
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#
85e7d1e9 |
| 13-Sep-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
Architecturally, for an M-profile CPU with the LOB feature the LTPSIZE field in FPDSCR is always constant 4. QEMU's implementation
target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
Architecturally, for an M-profile CPU with the LOB feature the LTPSIZE field in FPDSCR is always constant 4. QEMU's implementation enforces this everywhere, except that we don't check that it is true in incoming migration data.
We're going to add come in gen_update_fp_context() which relies on the "always 4" property. Since this is TCG-only, we don't actually need to be robust to bogus incoming migration data, and the effect of it being wrong would be wrong code generation rather than a QEMU crash; but if it did ever happen somehow it would be very difficult to track down the cause. Add a check so that we fail the inbound migration if the FPDSCR.LTPSIZE value is incorrect.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210913095440.13462-3-peter.maydell@linaro.org
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Revision tags: v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0 |
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#
b26b5629 |
| 20-May-2021 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make FPSCR.LTPSIZE writable for MVE
The M-profile FPSCR has an LTPSIZE field, but if MVE is not implemented it is read-only and always reads as 4; this is how QEMU currently handles it.
target/arm: Make FPSCR.LTPSIZE writable for MVE
The M-profile FPSCR has an LTPSIZE field, but if MVE is not implemented it is read-only and always reads as 4; this is how QEMU currently handles it.
Make the field writable when MVE is implemented.
We can safely add the field to the MVE migration struct because currently no CPUs enable MVE and so the migration struct is never used.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210520152840.24453-8-peter.maydell@linaro.org
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