Revision tags: v2.11.1 |
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#
ef401601 |
| 23-Jan-2018 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Add SVE to migration state
Save the high parts of the Zregs and all of the Pregs. The ZCR_ELx registers are migrated via the CP mechanism.
Signed-off-by: Richard Henderson <richard.hend
target/arm: Add SVE to migration state
Save the high parts of the Zregs and all of the Pregs. The ZCR_ELx registers are migrated via the CP mechanism.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180123035349.24538-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
c39c2b90 |
| 09-Feb-2018 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Expand vector registers for SVE
Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg. The previous patches have made the change in representation relatively painless.
Reviewed-
target/arm: Expand vector registers for SVE
Change vfp.regs as a uint64_t to vfp.zregs as an ARMVectorReg. The previous patches have made the change in representation relatively painless.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180123035349.24538-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
3f68b8a5 |
| 25-Jan-2018 |
Richard Henderson <richard.henderson@linaro.org> |
target/arm: Change the type of vfp.regs
All direct users of this field want an integral value. Drop all of the extra casting between uint64_t and float64.
Signed-off-by: Richard Henderson <richard
target/arm: Change the type of vfp.regs
All direct users of this field want an integral value. Drop all of the extra casting between uint64_t and float64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180119045438.28582-6-richard.henderson@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: v2.10.2, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, v2.11.0-rc3, v2.11.0-rc2, v2.11.0-rc1, v2.11.0-rc0 |
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#
9901c576 |
| 06-Oct-2017 |
Peter Maydell <peter.maydell@linaro.org> |
nvic: Implement Security Attribution Unit registers
Implement the register interface for the SAU: SAU_CTRL, SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the actual behaviour is implemented here
nvic: Implement Security Attribution Unit registers
Implement the register interface for the SAU: SAU_CTRL, SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the actual behaviour is implemented here; registers just read back as written.
When the CPU definition for Cortex-M33 is eventually added, its initfn will set cpu->sau_sregion, in the same way that we currently set cpu->pmsav7_dregion for the M3 and M4.
Number of SAU regions is typically a configurable CPU parameter, but this patch doesn't provide a QEMU CPU property for it. We can easily add one when we have a board that requires it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-14-git-send-email-peter.maydell@linaro.org
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#
bed079da |
| 06-Oct-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Add new-in-v8M SFSR and SFAR
Add the new M profile Secure Fault Status Register and Secure Fault Address Register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: R
target/arm: Add new-in-v8M SFSR and SFAR
Add the new M profile Secure Fault Status Register and Secure Fault Address Register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1506092407-26985-10-git-send-email-peter.maydell@linaro.org
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Revision tags: v2.10.1 |
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#
44b1ff31 |
| 25-Sep-2017 |
Dr. David Alan Gilbert <dgilbert@redhat.com> |
migration: pre_save return int
Modify the pre_save method on VMStateDescription to return an int rather than void so that it potentially can fail.
Changed zillions of devices to make them return 0;
migration: pre_save return int
Modify the pre_save method on VMStateDescription to return an int rather than void so that it potentially can fail.
Changed zillions of devices to make them return 0; the only case I've made it return non-0 is hw/intc/s390_flic_kvm.c that already had an error_report/return case.
Note: If you add an error exit in your pre_save you must emit an error_report to say why.
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20170925112917.21340-2-dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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Revision tags: v2.9.1 |
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#
fb602cb7 |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement BXNS, and banked stack pointers
Implement the BXNS v8M instruction, which is like BX but will do a jump-and-switch-to-NonSecure if the branch target address has bit 0 clear.
T
target/arm: Implement BXNS, and banked stack pointers
Implement the BXNS v8M instruction, which is like BX but will do a jump-and-switch-to-NonSecure if the branch target address has bit 0 clear.
This is the first piece of code which implements "switch to the other security state", so the commit also includes the code to switch the stack pointers around, which is the only complicated part of switching security state.
BLXNS is more complicated than just "BXNS but set the link register", so we leave it for a separate commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-21-git-send-email-peter.maydell@linaro.org
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#
334e8dad |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make CFSR register banked for v8M
Make the CFSR register banked if v8M security extensions are enabled.
Not all the bits in this register are banked: the BFSR bits [15:8] are shared bet
target/arm: Make CFSR register banked for v8M
Make the CFSR register banked if v8M security extensions are enabled.
Not all the bits in this register are banked: the BFSR bits [15:8] are shared between S and NS, and we store them in the NS copy of the register.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-19-git-send-email-peter.maydell@linaro.org
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#
c51a5cfc |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make MMFAR banked for v8M
Make the MMFAR register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <
target/arm: Make MMFAR banked for v8M
Make the MMFAR register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-18-git-send-email-peter.maydell@linaro.org
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#
9d40cd8a |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make CCR register banked for v8M
Make the CCR register banked if v8M security extensions are enabled.
This is slightly more complicated than the other "add banking" patches because ther
target/arm: Make CCR register banked for v8M
Make the CCR register banked if v8M security extensions are enabled.
This is slightly more complicated than the other "add banking" patches because there is one bit in the register which is not banked. We keep the live data in the NS copy of the register, and adjust it on register reads and writes. (Since we don't currently implement the behaviour that the bit controls, there is nowhere else that needs to care.)
This patch includes the enforcement of the bits which are newly RES1 in ARMv8M.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1503414539-28762-17-git-send-email-peter.maydell@linaro.org
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#
ecf5e8ea |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make MPU_CTRL register banked for v8M
Make the MPU_CTRL register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Rich
target/arm: Make MPU_CTRL register banked for v8M
Make the MPU_CTRL register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
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#
1bc04a88 |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make MPU_RNR register banked for v8M
Make the MPU_RNR register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richar
target/arm: Make MPU_RNR register banked for v8M
Make the MPU_RNR register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-15-git-send-email-peter.maydell@linaro.org
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#
62c58ee0 |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled.
We can freely add more items to vmstate_m_security w
target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled.
We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-14-git-send-email-peter.maydell@linaro.org
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#
4125e6fe |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.mayd
target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-13-git-send-email-peter.maydell@linaro.org
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#
45db7ba6 |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make VTOR register banked for v8M
Make the VTOR register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Hend
target/arm: Make VTOR register banked for v8M
Make the VTOR register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-12-git-send-email-peter.maydell@linaro.org
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#
8bfc26ea |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make CONTROL register banked for v8M
Make the CONTROL register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richar
target/arm: Make CONTROL register banked for v8M
Make the CONTROL register banked if v8M security extensions are enabled.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-10-git-send-email-peter.maydell@linaro.org
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#
42a6686b |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make FAULTMASK register banked for v8M
Make the FAULTMASK register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new AIRCR.PR
target/arm: Make FAULTMASK register banked for v8M
Make the FAULTMASK register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to be restricted).
This patch includes the code to determine for v8M which copy of FAULTMASK should be updated on exception exit; further changes will be required to the exception exit code in general to support v8M, so this is just a small piece of that.
The v8M ARM ARM introduces a notation where individual paragraphs are labelled with R (for rule) or I (for information) followed by a random group of subscript letters. In comments where we want to refer to a particular part of the manual we use this convention, which should be more stable across document revisions than using section or page numbers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-9-git-send-email-peter.maydell@linaro.org
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#
6d804834 |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make PRIMASK register banked for v8M
Make the PRIMASK register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new AIRCR.PRIS b
target/arm: Make PRIMASK register banked for v8M
Make the PRIMASK register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to be restricted).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-8-git-send-email-peter.maydell@linaro.org
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#
acf94941 |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Make BASEPRI register banked for v8M
Make the BASEPRI register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new AIRCR.PRIS b
target/arm: Make BASEPRI register banked for v8M
Make the BASEPRI register banked if v8M security extensions are enabled.
Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to be restricted).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-7-git-send-email-peter.maydell@linaro.org
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#
1e577cc7 |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Add state field, feature bit and migration for v8M secure state
As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the
target/arm: Add state field, feature bit and migration for v8M secure state
As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the CPU state field that indicates whether the CPU is currently in the secure state * add a migration subsection for this new state (we will add the Secure copies of banked register state to this subsection in later patches) * add a #define for the one new-in-v8M exception type * make the CPU debug log print S/NS status
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-4-git-send-email-peter.maydell@linaro.org
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#
0e1a46bb |
| 07-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Implement ARMv8M's PMSAv8 registers
As part of ARMv8M, we need to add support for the PMSAv8 MPU architecture.
PMSAv8 differs from PMSAv7 both in register/data layout (for instance usin
target/arm: Implement ARMv8M's PMSAv8 registers
As part of ARMv8M, we need to add support for the PMSAv8 MPU architecture.
PMSAv8 differs from PMSAv7 both in register/data layout (for instance using base and limit registers rather than base and size) and also in behaviour (for example it does not have subregions); rather than trying to wedge it into the existing PMSAv7 code and data structures, we define separate ones.
This commit adds the data structures which hold the state for a PMSAv8 MPU and the register interface to it. The implementation of the MPU behaviour will be added in a subsequent commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1503414539-28762-2-git-send-email-peter.maydell@linaro.org
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#
eeade001 |
| 04-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
For M profile the XPSR is a similar but not identical format to the A profile CPSR/SPSR. (For instance the Thumb bit is in a dif
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
For M profile the XPSR is a similar but not identical format to the A profile CPSR/SPSR. (For instance the Thumb bit is in a different place.) For guest accesses we make the M profile code go through xpsr_read() and xpsr_write() which handle the different layout. However for migration we use cpsr_read() and cpsr_write() to marshal state into and out of the migration data stream. This is pretty confusing and works more by luck than anything else. Make M profile migration use xpsr_read() and xpsr_write() instead.
The most complicated part of this is handling the possibility that the migration source is an older QEMU which hands us a CPSR format value; helpfully we can always tell the two apart.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1501692241-23310-11-git-send-email-peter.maydell@linaro.org
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#
e6ae5981 |
| 04-Sep-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
We currently store the M profile CPU register state PRIMASK and FAULTMASK in the daif field of the CPU state in its I and F bits. This
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
We currently store the M profile CPU register state PRIMASK and FAULTMASK in the daif field of the CPU state in its I and F bits. This is a legacy from the original implementation, which tried to share the cpu_exec_interrupt code between A profile and M profile. We've since separated out the two cases because they are significantly different, so now there is no common code between M and A profile which looks at env->daif: all the uses are either in A-only or M-only code paths. Sharing the state fields now is just confusing, and will make things awkward when we implement v8M, where the PRIMASK and FAULTMASK registers are banked between security states.
Switch M profile over to using v7m.faultmask and v7m.primask fields for these registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1501692241-23310-10-git-send-email-peter.maydell@linaro.org
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Revision tags: v2.10.0, v2.10.0-rc4, v2.10.0-rc3, v2.10.0-rc2, v2.10.0-rc1 |
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#
f1a46940 |
| 27-Jul-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Migrate MPU_RNR register state for M profile cores
The PMSAv7 region number register is migrated for R profile cores using the cpreg scheme, but M profile doesn't use cpregs, and so we w
target/arm: Migrate MPU_RNR register state for M profile cores
The PMSAv7 region number register is migrated for R profile cores using the cpreg scheme, but M profile doesn't use cpregs, and so we weren't migrating the MPU_RNR register state at all. Fix that by adding a migration subsection for the M profile case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1501153150-19984-6-git-send-email-peter.maydell@linaro.org
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#
8531eb4f |
| 27-Jul-2017 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
Almost all of the PMSAv7 state is in the pmsav7 substruct of the ARM CPU state structure. The exception is the region number register, which is in cp15.
target/arm: Rename cp15.c6_rgnr to pmsav7.rnr
Almost all of the PMSAv7 state is in the pmsav7 substruct of the ARM CPU state structure. The exception is the region number register, which is in cp15.c6_rgnr. This exception is a bit odd for M profile, which otherwise generally does not store state in the cp15 substruct.
Rename cp15.c6_rgnr to pmsav7.rnr accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1501153150-19984-4-git-send-email-peter.maydell@linaro.org
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