Revision tags: v8.1.2 |
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#
24b34590 |
| 13-Oct-2023 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: check intercept for XSETBV
Note that this intercept is special; it is checked before the #GP exception.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v8.1.2 |
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#
24b34590 |
| 13-Oct-2023 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: check intercept for XSETBV
Note that this intercept is special; it is checked before the #GP exception.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v8.1.2 |
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#
24b34590 |
| 13-Oct-2023 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: check intercept for XSETBV
Note that this intercept is special; it is checked before the #GP exception.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v8.1.2 |
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#
24b34590 |
| 13-Oct-2023 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: check intercept for XSETBV
Note that this intercept is special; it is checked before the #GP exception.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0, v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0, v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1, v6.1.0, v6.1.0-rc4, v6.1.0-rc3 |
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#
52fb8ad3 |
| 09-Aug-2021 |
Lara Lazier <laramglazier@gmail.com> |
target/i386: Added vVMLOAD and vVMSAVE feature
The feature allows the VMSAVE and VMLOAD instructions to execute in guest mode without causing a VMEXIT. (APM2 15.33.1)
Signed-off-by: Lara Lazier <la
target/i386: Added vVMLOAD and vVMSAVE feature
The feature allows the VMSAVE and VMLOAD instructions to execute in guest mode without causing a VMEXIT. (APM2 15.33.1)
Signed-off-by: Lara Lazier <laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v6.1.0-rc2 |
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#
900eeca5 |
| 30-Jul-2021 |
Lara Lazier <laramglazier@gmail.com> |
target/i386: Added VGIF feature
VGIF allows STGI and CLGI to execute in guest mode and control virtual interrupts in guest mode. When the VGIF feature is enabled then: * executing STGI in the guest
target/i386: Added VGIF feature
VGIF allows STGI and CLGI to execute in guest mode and control virtual interrupts in guest mode. When the VGIF feature is enabled then: * executing STGI in the guest sets bit 9 of the VMCB offset 60h. * executing CLGI in the guest clears bit 9 of the VMCB offset 60h.
Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210730070742.9674-1-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v6.1.0-rc1, v6.1.0-rc0 |
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#
533883fd |
| 06-Jul-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: fix exceptions for MOV to DR
Use raise_exception_ra (without error code) when raising the illegal opcode operation; raise #GP when setting bits 63:32 of DR6 or DR7.
Move helper_get_dr
target/i386: fix exceptions for MOV to DR
Use raise_exception_ra (without error code) when raising the illegal opcode operation; raise #GP when setting bits 63:32 of DR6 or DR7.
Move helper_get_dr to sysemu/ since it is a privileged instruction that is not needed on user-mode emulators.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
acf23ffb |
| 05-Jul-2021 |
Lara Lazier <laramglazier@gmail.com> |
target/i386: Added DR6 and DR7 consistency checks
DR6[63:32] and DR7[63:32] are reserved and need to be zero. (AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier <laramgla
target/i386: Added DR6 and DR7 consistency checks
DR6[63:32] and DR7[63:32] are reserved and need to be zero. (AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210705081802.18960-3-laramglazier@gmail.com> [Ignore for 32-bit builds. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
481077b2 |
| 05-Jul-2021 |
Lara Lazier <laramglazier@gmail.com> |
target/i386: Added MSRPM and IOPM size check
The address of the last entry in the MSRPM and in the IOPM must be smaller than the largest physical address. (APM2 15.10-15.11)
Signed-off-by: Lara Laz
target/i386: Added MSRPM and IOPM size check
The address of the last entry in the MSRPM and in the IOPM must be smaller than the largest physical address. (APM2 15.10-15.11)
Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210705081802.18960-2-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
498df2a7 |
| 16-Jun-2021 |
Lara Lazier <laramglazier@gmail.com> |
target/i386: Added consistency checks for CR0
The combination of unset CD and set NW bit in CR0 is illegal. CR0[63:32] are also reserved and need to be zero. (AMD64 Architecture Programmer's Manual,
target/i386: Added consistency checks for CR0
The combination of unset CD and set NW bit in CR0 is illegal. CR0[63:32] are also reserved and need to be zero. (AMD64 Architecture Programmer's Manual, V2, 15.5)
Signed-off-by: Lara Lazier <laramglazier@gmail.com> Message-Id: <20210616123907.17765-4-laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v6.0.0, v6.0.0-rc5, v6.0.0-rc4, v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0 |
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#
616a89ea |
| 26-Feb-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: move paging mode constants from SVM to cpu.h
We will reuse the page walker for both SVM and regular accesses. To do so we will build a function that receives the currently active pagin
target/i386: move paging mode constants from SVM to cpu.h
We will reuse the page walker for both SVM and regular accesses. To do so we will build a function that receives the currently active paging mode; start by including in cpu.h the constants and the function to go from cr4/hflags/efer to the paging mode.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
6ed6b0d3 |
| 26-Feb-2021 |
Paolo Bonzini <pbonzini@redhat.com> |
target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constants
They are the same value, and are so by design.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v5.2.0, v5.2.0-rc4, v5.2.0-rc3, v5.2.0-rc2, v5.2.0-rc1, v5.2.0-rc0, v5.0.1, v5.1.0, v5.1.0-rc3, v5.1.0-rc2, v5.1.0-rc1, v5.1.0-rc0 |
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#
a2d57703 |
| 29-Jun-2020 |
Alexander Boettcher <alexander.boettcher@genode-labs.com> |
tcg/svm: use host cr4 during NPT page table walk
During a page table walk of TCG+SVM the code in target/i386/excp_helper.c get_hphys() uses the cr4 register of the guest instead of the hypervisor to
tcg/svm: use host cr4 during NPT page table walk
During a page table walk of TCG+SVM the code in target/i386/excp_helper.c get_hphys() uses the cr4 register of the guest instead of the hypervisor to check for the PSE bit. In the test case we have, the guest have not enabled (yet) the PSE bit and so the page table walk results in a wrong host physical address resolution and wrong content read by the guest.
Attached patch is against 4.2.1, but works also on 3.1.0. It fixes the issue for our automated testcase, which is a 32bit hypervisor w/o PAE support running a guest VM with tcg+svm.
The test worked beforehand up to qemu 2.12, started to fail with qemu 3.0 and later. The added TCG/SVM NPT commit seems to introduce the regression.
In case someone want to try to reproduce it, the iso is at [0], the good case is [1] and the failing case is [2]. The used commandline is:
qemu-system-i386 -no-kvm -nographic -cpu phenom -m 512 -machine q35 -cdrom seoul-vmm-test.iso
[0] https://depot.genode.org/alex-ab/images/seoul-vmm-test.iso [1] https://depot.genode.org/alex-ab/images/seoul-vmm-good.txt [2] https://depot.genode.org/alex-ab/images/seoul-vmm-bad.txt
Signed-off-by: Alexander Boettcher <alexander.boettcher@genode-labs.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v4.2.1, v5.0.0, v5.0.0-rc4, v5.0.0-rc3, v5.0.0-rc2, v5.0.0-rc1, v5.0.0-rc0, v4.2.0, v4.2.0-rc5, v4.2.0-rc4, v4.2.0-rc3, v4.2.0-rc2, v4.1.1, v4.2.0-rc1, v4.2.0-rc0, v4.0.1, v3.1.1.1, v4.1.0, v4.1.0-rc5, v4.1.0-rc4, v3.1.1, v4.1.0-rc3, v4.1.0-rc2, v4.1.0-rc1, v4.1.0-rc0, v4.0.0, v4.0.0-rc4, v3.0.1, v4.0.0-rc3, v4.0.0-rc2, v4.0.0-rc1, v4.0.0-rc0, v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0, v3.0.0, v3.0.0-rc4, v2.12.1, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, v3.0.0-rc0 |
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#
fe441054 |
| 30-Jun-2018 |
Jan Kiszka <jan.kiszka@siemens.com> |
target-i386: Add NPT support
This implements NPT suport for SVM by hooking into x86_cpu_handle_mmu_fault where it reads the stage-1 page table. Whether we need to perform this 2nd stage translation,
target-i386: Add NPT support
This implements NPT suport for SVM by hooking into x86_cpu_handle_mmu_fault where it reads the stage-1 page table. Whether we need to perform this 2nd stage translation, and how, is decided during vmrun and stored in hflags2, along with nested_cr3 and nested_pg_mode.
As get_hphys performs a direct cpu_vmexit in case of NPT faults, we need retaddr in that function. To avoid changing the signature of cpu_handle_mmu_fault, this passes the value from tlb_fill to get_hphys via the CPU state.
This was tested successfully via the Jailhouse hypervisor.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-Id: <567473a0-6005-5843-4c73-951f476085ca@web.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v2.11.2, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, v2.11.1, v2.10.2, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, v2.11.0-rc3, v2.11.0-rc2, v2.11.0-rc1, v2.11.0-rc0, v2.10.1, v2.9.1, v2.10.0, v2.10.0-rc4, v2.10.0-rc3, v2.10.0-rc2, v2.10.0-rc1, v2.10.0-rc0, v2.8.1.1, v2.9.0, v2.9.0-rc5, v2.9.0-rc4, v2.9.0-rc3, v2.8.1, v2.9.0-rc2, v2.9.0-rc1, v2.9.0-rc0, v2.7.1, v2.8.0, v2.8.0-rc4, v2.8.0-rc3, v2.8.0-rc2, v2.8.0-rc1, v2.8.0-rc0 |
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#
fcf5ef2a |
| 11-Oct-2016 |
Thomas Huth <thuth@redhat.com> |
Move target-* CPU file into a target/ folder
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V,
Move target-* CPU file into a target/ folder
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead.
Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [crisµblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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