Revision tags: v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10, v8.2.1, v8.1.5, v7.2.9 |
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#
8f054d9e |
| 23-Jan-2024 |
Nicholas Piggin <npiggin@gmail.com> |
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@li
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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Revision tags: v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10, v8.2.1, v8.1.5, v7.2.9 |
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#
8f054d9e |
| 23-Jan-2024 |
Nicholas Piggin <npiggin@gmail.com> |
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@li
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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Revision tags: v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10, v8.2.1, v8.1.5, v7.2.9 |
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#
8f054d9e |
| 23-Jan-2024 |
Nicholas Piggin <npiggin@gmail.com> |
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@li
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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Revision tags: v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10, v8.2.1, v8.1.5, v7.2.9 |
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#
8f054d9e |
| 23-Jan-2024 |
Nicholas Piggin <npiggin@gmail.com> |
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@li
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
show more ...
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Revision tags: v9.0.0-rc2, v9.0.0-rc1, v9.0.0-rc0, v8.2.2, v7.2.10, v8.2.1, v8.1.5, v7.2.9 |
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#
8f054d9e |
| 23-Jan-2024 |
Nicholas Piggin <npiggin@gmail.com> |
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@li
ppc: Drop support for POWER9 and POWER10 DD1 chips
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of any use in QEMU. Remove them.
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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#
5bfb75f1 |
| 17-Jan-2024 |
Thomas Huth <thuth@redhat.com> |
target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules
The character "+" is now forbidden in QOM device names (see commit b447378e1217 - "Limit type names to alphanumerical and s
target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules
The character "+" is now forbidden in QOM device names (see commit b447378e1217 - "Limit type names to alphanumerical and some few special characters"). For the "power5+" and "power7+" CPU names, there is currently a hack in type_name_is_valid() to still allow them for compatibility reasons. However, there is a much nicer solution for this: Simply use aliases! This way we can still support the old names without the need for the ugly hack in type_name_is_valid().
Message-ID: <20240117141054.73841-2-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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Revision tags: v8.1.4, v7.2.8, v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0, v8.1.2, v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3 |
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#
277ee172 |
| 15-May-2023 |
Nicholas Piggin <npiggin@gmail.com> |
target/ppc: Add POWER9 DD2.2 model
POWER9 DD2.1 and earlier had significant limitations when running KVM, including lack of "mixed mode" MMU support (ability to run HPT and RPT mode on threads of th
target/ppc: Add POWER9 DD2.2 model
POWER9 DD2.1 and earlier had significant limitations when running KVM, including lack of "mixed mode" MMU support (ability to run HPT and RPT mode on threads of the same core), and a translation prefetch issue which is worked around by disabling "AIL" mode for the guest.
These processors are not widely available, and it's difficult to deal with all these quirks in qemu +/- KVM, so create a POWER9 DD2.2 CPU and make it the default POWER9 CPU.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Message-Id: <20230515160201.394587-1-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Revision tags: v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
0b83377f |
| 03-Jul-2022 |
Pali Rohár <pali@kernel.org> |
target/ppc: Fix MPC8555 and MPC8560 core type to e500v1
Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") changed core type of MPC8555 and MPC8560 from e500v1 to e500v2.
target/ppc: Fix MPC8555 and MPC8560 core type to e500v1
Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") changed core type of MPC8555 and MPC8560 from e500v1 to e500v2.
But both MPC8555 and MPC8560 have just e500v1 cores, there are no features of e500v2 cores. It can be verified by reading NXP documentations: https://www.nxp.com/docs/en/data-sheet/MPC8555EEC.pdf https://www.nxp.com/docs/en/data-sheet/MPC8560EC.pdf https://www.nxp.com/docs/en/reference-manual/MPC8555ERM.pdf https://www.nxp.com/docs/en/reference-manual/MPC8560RM.pdf
Therefore fix core type of MPC8555 and MPC8560 back to e500v1.
Just for completeness, here is list of all Motorola/Freescale/NXP processors which were released and have e500v1 or e500v2 cores:
e500v1: MPC8540 MPC8541 MPC8555 MPC8560
e500v2: BSC9131 BSC9132 C291 C292 C293 MPC8533 MPC8535 MPC8536 MPC8543 MPC8544 MPC8545 MPC8547 MPC8548 MPC8567 MPC8568 MPC8569 MPC8572 P1010 P1011 P1012 P1013 P1014 P1015 P1016 P1020 P1021 P1022 P1024 P1025 P2010 P2020
Sorted alphabetically; not by release date / generation / feature set. All this is from public information available on NXP website.
Seems that qemu has support only for some subset of MPC85xx processors. Historically processors with e500 cores have mpc85xx family codename and lot of software have them in mpc85xx architecture subdirectory.
Note that GCC uses -mcpu=8540 option for specifying e500v1 core and -mcpu=8548 option for specifying e500v2 core.
So sometimes (mpc)8540 is alias for e500v1 and (mpc)8548 is alias for e500v2.
Fixes: 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220703195029.23793-1-pali@kernel.org> [danielhb: added more context in the commit msg] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
78866059 |
| 05-Jul-2022 |
Thomas Huth <thuth@redhat.com> |
target/ppc/cpu-models: Remove the "default" CPU alias
QEMU emulates a *lot* of PowerPC-based machines - having a CPU that is named "default" and cannot be used with most of those machines sounds jus
target/ppc/cpu-models: Remove the "default" CPU alias
QEMU emulates a *lot* of PowerPC-based machines - having a CPU that is named "default" and cannot be used with most of those machines sounds just wrong. Thus let's remove this old and confusing alias now.
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220705151030.662140-1-thuth@redhat.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
c7e89de1 |
| 28-Jun-2022 |
Murilo Opsfelder Araujo <muriloo@linux.ibm.com> |
target/ppc: Return default CPU for max CPU
All ppc CPUs represent hardware that exists in the real world, i.e.: we do not have a "max" CPU with all possible emulated features enabled. Return the def
target/ppc: Return default CPU for max CPU
All ppc CPUs represent hardware that exists in the real world, i.e.: we do not have a "max" CPU with all possible emulated features enabled. Return the default CPU type for the machine because that has greater chance of being useful as the "max" CPU.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038 Cc: Cédric Le Goater <clg@kaod.org> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Greg Kurz <groug@kaod.org> Cc: Matheus K. Ferst <matheus.ferst@eldorado.org.br> Cc: Thomas Huth <thuth@redhat.com> Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220628205513.81917-1-muriloo@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Revision tags: v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0, v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
0b83377f |
| 03-Jul-2022 |
Pali Rohár <pali@kernel.org> |
target/ppc: Fix MPC8555 and MPC8560 core type to e500v1
Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") changed core type of MPC8555 and MPC8560 from e500v1 to e500v2.
target/ppc: Fix MPC8555 and MPC8560 core type to e500v1
Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") changed core type of MPC8555 and MPC8560 from e500v1 to e500v2.
But both MPC8555 and MPC8560 have just e500v1 cores, there are no features of e500v2 cores. It can be verified by reading NXP documentations: https://www.nxp.com/docs/en/data-sheet/MPC8555EEC.pdf https://www.nxp.com/docs/en/data-sheet/MPC8560EC.pdf https://www.nxp.com/docs/en/reference-manual/MPC8555ERM.pdf https://www.nxp.com/docs/en/reference-manual/MPC8560RM.pdf
Therefore fix core type of MPC8555 and MPC8560 back to e500v1.
Just for completeness, here is list of all Motorola/Freescale/NXP processors which were released and have e500v1 or e500v2 cores:
e500v1: MPC8540 MPC8541 MPC8555 MPC8560
e500v2: BSC9131 BSC9132 C291 C292 C293 MPC8533 MPC8535 MPC8536 MPC8543 MPC8544 MPC8545 MPC8547 MPC8548 MPC8567 MPC8568 MPC8569 MPC8572 P1010 P1011 P1012 P1013 P1014 P1015 P1016 P1020 P1021 P1022 P1024 P1025 P2010 P2020
Sorted alphabetically; not by release date / generation / feature set. All this is from public information available on NXP website.
Seems that qemu has support only for some subset of MPC85xx processors. Historically processors with e500 cores have mpc85xx family codename and lot of software have them in mpc85xx architecture subdirectory.
Note that GCC uses -mcpu=8540 option for specifying e500v1 core and -mcpu=8548 option for specifying e500v2 core.
So sometimes (mpc)8540 is alias for e500v1 and (mpc)8548 is alias for e500v2.
Fixes: 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220703195029.23793-1-pali@kernel.org> [danielhb: added more context in the commit msg] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
show more ...
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#
78866059 |
| 05-Jul-2022 |
Thomas Huth <thuth@redhat.com> |
target/ppc/cpu-models: Remove the "default" CPU alias
QEMU emulates a *lot* of PowerPC-based machines - having a CPU that is named "default" and cannot be used with most of those machines sounds jus
target/ppc/cpu-models: Remove the "default" CPU alias
QEMU emulates a *lot* of PowerPC-based machines - having a CPU that is named "default" and cannot be used with most of those machines sounds just wrong. Thus let's remove this old and confusing alias now.
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220705151030.662140-1-thuth@redhat.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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#
c7e89de1 |
| 28-Jun-2022 |
Murilo Opsfelder Araujo <muriloo@linux.ibm.com> |
target/ppc: Return default CPU for max CPU
All ppc CPUs represent hardware that exists in the real world, i.e.: we do not have a "max" CPU with all possible emulated features enabled. Return the def
target/ppc: Return default CPU for max CPU
All ppc CPUs represent hardware that exists in the real world, i.e.: we do not have a "max" CPU with all possible emulated features enabled. Return the default CPU type for the machine because that has greater chance of being useful as the "max" CPU.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038 Cc: Cédric Le Goater <clg@kaod.org> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Greg Kurz <groug@kaod.org> Cc: Matheus K. Ferst <matheus.ferst@eldorado.org.br> Cc: Thomas Huth <thuth@redhat.com> Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220628205513.81917-1-muriloo@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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Revision tags: v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0 |
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#
005b69fd |
| 09-Feb-2022 |
Cédric Le Goater <clg@kaod.org> |
target/ppc: Remove PowerPC 601 CPUs
The PowerPC 601 processor is the first generation of processors to implement the PowerPC architecture. It was designed as a bridge processor and also could execut
target/ppc: Remove PowerPC 601 CPUs
The PowerPC 601 processor is the first generation of processors to implement the PowerPC architecture. It was designed as a bridge processor and also could execute most of the instructions of the previous POWER architecture. It was found on the first Macs and IBM RS/6000 workstations.
There is not much interest in keeping the CPU model of this POWER-PowerPC bridge processor. We have the 603 and 604 CPU models of the 60x family which implement the complete PowerPC instruction set.
Cc: "Hervé Poussineau" <hpoussin@reactos.org> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203142756.1302515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
4537d62d |
| 24-Jan-2022 |
Cédric Le Goater <clg@kaod.org> |
target/ppc: Remove support for the PowerPC 602 CPU
The 602 was derived from the PowerPC 603, for the gaming market it seems. It was hardly used and no firmware supporting the CPU could be found. Dro
target/ppc: Remove support for the PowerPC 602 CPU
The 602 was derived from the PowerPC 603, for the gaming market it seems. It was hardly used and no firmware supporting the CPU could be found. Drop support.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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fe072a99 |
| 18-Jan-2022 |
Cédric Le Goater <clg@kaod.org> |
target/ppc: Fix 7448 support
The 7448 CPU is an evolution of the PowerPC 7447A and the last of the G4 family. Change its family to reflect correctly its features. This fixes Linux boot.
Cc: Fabiano
target/ppc: Fix 7448 support
The 7448 CPU is an evolution of the PowerPC 7447A and the last of the G4 family. Change its family to reflect correctly its features. This fixes Linux boot.
Cc: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220117092555.1616512-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
328c95fc |
| 18-Jan-2022 |
Cédric Le Goater <clg@kaod.org> |
target/ppc: Finish removal of 401/403 CPUs
Commit c8f49e6b938e ("target/ppc: remove 401/403 CPUs") left a few things behind.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gi
target/ppc: Finish removal of 401/403 CPUs
Commit c8f49e6b938e ("target/ppc: remove 401/403 CPUs") left a few things behind.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20220117091541.1615807-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220118104150.1899661-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v6.1.1 |
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#
c8f49e6b |
| 17-Dec-2021 |
Cédric Le Goater <clg@kaod.org> |
target/ppc: remove 401/403 CPUs
They have been there since 2007 without any board using them, most were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater <clg@kaod.org> Revi
target/ppc: remove 401/403 CPUs
They have been there since 2007 without any board using them, most were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211202191108.1291515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Revision tags: v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1, v6.1.0, v6.1.0-rc4, v6.1.0-rc3 |
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#
363fd548 |
| 09-Aug-2021 |
Cédric Le Goater <clg@kaod.org> |
ppc: Add a POWER10 DD2 CPU
The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have HAIL but since it does not break the modeling and that we don't plan to support DD1, modify the LPCR mas
ppc: Add a POWER10 DD2 CPU
The POWER10 DD2 CPU adds an extra LPCR[HAIL] bit. DD1 doesn't have HAIL but since it does not break the modeling and that we don't plan to support DD1, modify the LPCR mask of all the POWER10 family.
Setting the HAIL bit is a requirement to support the scv instruction on PowerNV POWER10 platforms since glibc-2.33.
Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210809134547.689560-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Revision tags: v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0, v6.0.0, v6.0.0-rc5, v6.0.0-rc4, v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0, v5.2.0, v5.2.0-rc4, v5.2.0-rc3, v5.2.0-rc2, v5.2.0-rc1, v5.2.0-rc0 |
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#
6bd039cd |
| 19-Oct-2020 |
Chetan Pant <chetan4windows@gmail.com> |
powerpc tcg: Fix Lesser GPL version number
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurre
powerpc tcg: Fix Lesser GPL version number
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section.
Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201019061126.3102-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
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Revision tags: v5.0.1, v5.1.0, v5.1.0-rc3, v5.1.0-rc2, v5.1.0-rc1, v5.1.0-rc0, v4.2.1, v5.0.0, v5.0.0-rc4, v5.0.0-rc3, v5.0.0-rc2, v5.0.0-rc1, v5.0.0-rc0, v4.2.0, v4.2.0-rc5 |
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7d37b274 |
| 05-Dec-2019 |
Cédric Le Goater <clg@kaod.org> |
target/ppc: Add POWER10 DD1.0 model information
This includes in QEMU a new CPU model for the POWER10 processor with the same capabilities of a POWER9 process. The model will be extended when suppor
target/ppc: Add POWER10 DD1.0 model information
This includes in QEMU a new CPU model for the POWER10 processor with the same capabilities of a POWER9 process. The model will be extended when support is completed.
Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191205184454.10722-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Revision tags: v4.2.0-rc4, v4.2.0-rc3, v4.2.0-rc2, v4.1.1, v4.2.0-rc1, v4.2.0-rc0, v4.0.1, v3.1.1.1, v4.1.0, v4.1.0-rc5, v4.1.0-rc4, v3.1.1, v4.1.0-rc3, v4.1.0-rc2, v4.1.0-rc1, v4.1.0-rc0 |
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0b8fa32f |
| 23-May-2019 |
Markus Armbruster <armbru@redhat.com> |
Include qemu/module.h where needed, drop it from qemu-common.h
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-4-armbru@redhat.com> [Rebased with conflicts res
Include qemu/module.h where needed, drop it from qemu-common.h
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-4-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for hw/usb/dev-hub.c hw/misc/exynos4210_rng.c hw/misc/bcm2835_rng.c hw/misc/aspeed_scu.c hw/display/virtio-vga.c hw/arm/stm32f205_soc.c; ui/cocoa.m fixed up]
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Revision tags: v4.0.0, v4.0.0-rc4, v3.0.1, v4.0.0-rc3, v4.0.0-rc2, v4.0.0-rc1 |
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b93745bb |
| 21-Mar-2019 |
David Gibson <david@gibson.dropbear.id.au> |
target/ppc: Style fixes for ppc-models.[ch]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
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Revision tags: v4.0.0-rc0, v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0 |
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9545f2e1 |
| 07-Sep-2018 |
Thomas Huth <thuth@redhat.com> |
target/ppc/cpu-models: Re-group the 970 CPUs together again
The addition of the POWER9 CPUs divided the entries for the 970 CPUs, which is a little bit confusing when you look at the code. So let's
target/ppc/cpu-models: Re-group the 970 CPUs together again
The addition of the POWER9 CPUs divided the entries for the 970 CPUs, which is a little bit confusing when you look at the code. So let's re-group the 970 CPUs together again, and since these chips have been based on the POWER4 processor, move them also in front of the POWER5 chips now.
Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Revision tags: v3.0.0, v3.0.0-rc4, v2.12.1, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, v3.0.0-rc0, v2.11.2, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, v2.11.1, v2.10.2, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, v2.11.0-rc3, v2.11.0-rc2, v2.11.0-rc1, v2.11.0-rc0 |
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1ed9c8af |
| 06-Oct-2017 |
David Gibson <david@gibson.dropbear.id.au> |
target/ppc: Add POWER9 DD2.0 model information
At the moment the only POWER9 model which is listed in qemu is v1.0 (aka "DD1"). This is a very early (read, buggy) version which will never be releas
target/ppc: Add POWER9 DD2.0 model information
At the moment the only POWER9 model which is listed in qemu is v1.0 (aka "DD1"). This is a very early (read, buggy) version which will never be released to the public - it was included in qemu only for the convenience of those doing bringup on the early silicon. For bonus points, we actually had its PVR incorrect in the table (0x004e0000 instead of 0x004e0100). We also never actually implemented the differences in behaviour (read, bugs) that marked DD1 in qemu.
Now that we know the PVR for the substantially better v2.0 (DD2) chip, include it and make it the default POWER9 in qemu. For the time being we leave the DD1 definition in place for the poor souls (read, me) who still need to work with DD1 hardware.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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