Revision tags: v7.2.2, v8.0.0 |
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#
e1d084a8 |
| 18-Apr-2023 |
Rahul Pathak <rpathak@ventanamicro.com> |
target/riscv: add Ventana's Veyron V1 CPU
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs exclusively for the rv64 target. It's tested with the 'virt' board.
CPU specs and genera
target/riscv: add Ventana's Veyron V1 CPU
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs exclusively for the rv64 target. It's tested with the 'virt' board.
CPU specs and general information can be found here:
https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v7.2.2, v8.0.0 |
|
#
e1d084a8 |
| 18-Apr-2023 |
Rahul Pathak <rpathak@ventanamicro.com> |
target/riscv: add Ventana's Veyron V1 CPU
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs exclusively for the rv64 target. It's tested with the 'virt' board.
CPU specs and genera
target/riscv: add Ventana's Veyron V1 CPU
Add a virtual CPU for Ventana's first CPU named veyron-v1. It runs exclusively for the rv64 target. It's tested with the 'virt' board.
CPU specs and general information can be found here:
https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/
Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230418123624.16414-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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Revision tags: v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
95bd8daa |
| 31-Jan-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
RISC-V: Add initial support for T-Head C906
This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. v
RISC-V: Add initial support for T-Head C906
This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions).
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
|
#
95bd8daa |
| 31-Jan-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
RISC-V: Add initial support for T-Head C906
This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. v
RISC-V: Add initial support for T-Head C906
This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions).
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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