Revision tags: v8.2.2, v7.2.10 |
|
#
e231ec8f |
| 02-Feb-2024 |
Vadim Shakirov <vadim.shakirov@syntacore.com> |
target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit by privileged spec
Signed-off-by: Vadim Shakirov
target/riscv: mcountinhibit, mcounteren, scounteren, hcounteren is 32-bit
mcountinhibit, mcounteren, scounteren and hcounteren must always be 32-bit by privileged spec
Signed-off-by: Vadim Shakirov <vadim.shakirov@syntacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20240202113919.18236-1-vadim.shakirov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
742cc269 |
| 03-Feb-2024 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
target/riscv: Move misa_mxl_max to class
misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Re
target/riscv: Move misa_mxl_max to class
misa_mxl_max is common for all instances of a RISC-V CPU class so they are better put into class.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240203-riscv-v11-2-a23f4848a628@daynix.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v8.2.1, v8.1.5, v7.2.9, v8.1.4, v7.2.8 |
|
#
85b57d3d |
| 21-Dec-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/riscv: Constify VMState in machine.c
Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-1
target/riscv: Constify VMState in machine.c
Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231221031652.119827-16-richard.henderson@linaro.org>
show more ...
|
Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
|
#
69b3849b |
| 31-Oct-2023 |
Rob Bradford <rbradford@rivosinc.com> |
target/riscv: Add "pmu-mask" property to replace "pmu-num"
Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counter
target/riscv: Add "pmu-mask" property to replace "pmu-num"
Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counters.
The "pmu-num" property now generates a warning when used by the user on the command line.
Rather than storing the value for "pmu-num" convert it directly to the mask if it is specified (overwriting the default "pmu-mask" value) likewise the value is calculated from the mask if the property value is obtained.
In the unusual situation that both "pmu-mask" and "pmu-num" are provided then then the order on the command line determines which takes precedence (later overwriting earlier.)
Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231031154000.18134-5-rbradford@rivosinc.com> [Changes by AF - Fixup ext_zihpm logic after rebase ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v8.1.2 |
|
#
40336d5b |
| 16-Oct-2023 |
Rajnesh Kanwal <rkanwal@rivosinc.com> |
target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from HS-mode into VS-mode using hvien and hvip csrs. This also allows
target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from HS-mode into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering from HS-mode.
Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows HS-mode to assert virtual interrupts to VS-mode that have no connection to any real interrupt events.
This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level".
[0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231016111736.28721-7-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
1697837e |
| 16-Oct-2023 |
Rajnesh Kanwal <rkanwal@rivosinc.com> |
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from M-mode into S-mode using mvien and mvip csrs. IRQ filtering is a
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from M-mode into S-mode using mvien and mvip csrs. IRQ filtering is a use case of this change, i-e M-mode can stop delegating an interrupt to S-mode and instead enable it in MIE and receive those interrupts in M-mode and then selectively inject the interrupt using mvien and mvip.
Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows M-mode to assert virtual interrupts to S-mode that have no connection to any real interrupt events.
This is defined as part of the AIA specification [0], "5.3 Interrupt filtering and virtual interrupts for supervisor level".
[0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231016111736.28721-6-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v8.2.0, v8.2.0-rc4, v8.2.0-rc3, v8.2.0-rc2, v8.2.0-rc1, v7.2.7, v8.1.3, v8.2.0-rc0 |
|
#
69b3849b |
| 31-Oct-2023 |
Rob Bradford <rbradford@rivosinc.com> |
target/riscv: Add "pmu-mask" property to replace "pmu-num"
Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counter
target/riscv: Add "pmu-mask" property to replace "pmu-num"
Using a mask instead of the number of PMU devices supports the accurate emulation of platforms that have a discontinuous set of PMU counters.
The "pmu-num" property now generates a warning when used by the user on the command line.
Rather than storing the value for "pmu-num" convert it directly to the mask if it is specified (overwriting the default "pmu-mask" value) likewise the value is calculated from the mask if the property value is obtained.
In the unusual situation that both "pmu-mask" and "pmu-num" are provided then then the order on the command line determines which takes precedence (later overwriting earlier.)
Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231031154000.18134-5-rbradford@rivosinc.com> [Changes by AF - Fixup ext_zihpm logic after rebase ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v8.1.2 |
|
#
40336d5b |
| 16-Oct-2023 |
Rajnesh Kanwal <rkanwal@rivosinc.com> |
target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from HS-mode into VS-mode using hvien and hvip csrs. This also allows
target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from HS-mode into VS-mode using hvien and hvip csrs. This also allows for IRQ filtering from HS-mode.
Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows HS-mode to assert virtual interrupts to VS-mode that have no connection to any real interrupt events.
This is defined as part of the AIA specification [0], "6.3.2 Virtual interrupts for VS level".
[0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231016111736.28721-7-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
1697837e |
| 16-Oct-2023 |
Rajnesh Kanwal <rkanwal@rivosinc.com> |
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from M-mode into S-mode using mvien and mvip csrs. IRQ filtering is a
target/riscv: Add M-mode virtual interrupt and IRQ filtering support.
This change adds support for inserting virtual interrupts from M-mode into S-mode using mvien and mvip csrs. IRQ filtering is a use case of this change, i-e M-mode can stop delegating an interrupt to S-mode and instead enable it in MIE and receive those interrupts in M-mode and then selectively inject the interrupt using mvien and mvip.
Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows M-mode to assert virtual interrupts to S-mode that have no connection to any real interrupt events.
This is defined as part of the AIA specification [0], "5.3 Interrupt filtering and virtual interrupts for supervisor level".
[0]: https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-interrupts-1.0.pdf
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231016111736.28721-6-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3 |
|
#
9638cbde |
| 04-Apr-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/riscv: Restrict KVM-specific fields from ArchCPU
These fields shouldn't be accessed when KVM is not available.
Restrict the KVM timer migration state. Rename the KVM timer post_load() handle
target/riscv: Restrict KVM-specific fields from ArchCPU
These fields shouldn't be accessed when KVM is not available.
Restrict the KVM timer migration state. Rename the KVM timer post_load() handler accordingly, because cpu_post_load() is too generic.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230626232007.8933-3-philmd@linaro.org>
show more ...
|
Revision tags: v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0, v8.0.3, v7.2.4, v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3 |
|
#
9638cbde |
| 04-Apr-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
target/riscv: Restrict KVM-specific fields from ArchCPU
These fields shouldn't be accessed when KVM is not available.
Restrict the KVM timer migration state. Rename the KVM timer post_load() handle
target/riscv: Restrict KVM-specific fields from ArchCPU
These fields shouldn't be accessed when KVM is not available.
Restrict the KVM timer migration state. Rename the KVM timer post_load() handler accordingly, because cpu_post_load() is too generic.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230626232007.8933-3-philmd@linaro.org>
show more ...
|
#
c45eff30 |
| 05-Apr-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: Fix format for indentation
Fix identation problems, and try to use the same indentation strategy in the same file.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqi
target/riscv: Fix format for indentation
Fix identation problems, and try to use the same indentation strategy in the same file.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v7.2.1, v8.0.0-rc2 |
|
#
b3c5077b |
| 27-Mar-2023 |
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
target/riscv: Convert env->virt to a bool env->virt_enabled
Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei <zhiw
target/riscv: Convert env->virt to a bool env->virt_enabled
Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v8.0.0-rc1, v8.0.0-rc0 |
|
#
ce3af0bb |
| 07-Mar-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
c45eff30 |
| 05-Apr-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: Fix format for indentation
Fix identation problems, and try to use the same indentation strategy in the same file.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqi
target/riscv: Fix format for indentation
Fix identation problems, and try to use the same indentation strategy in the same file.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230405085813.40643-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v7.2.1, v8.0.0-rc2 |
|
#
b3c5077b |
| 27-Mar-2023 |
LIU Zhiwei <zhiwei_liu@linux.alibaba.com> |
target/riscv: Convert env->virt to a bool env->virt_enabled
Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei <zhiw
target/riscv: Convert env->virt to a bool env->virt_enabled
Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230325145348.1208-1-zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230327080858.39703-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
Revision tags: v8.0.0-rc1, v8.0.0-rc0 |
|
#
ce3af0bb |
| 07-Mar-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
1e2de2b8 |
| 22-Feb-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv/cpu: remove CPUArchState::features and friends
The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead.
Remove env->feature
target/riscv/cpu: remove CPUArchState::features and friends
The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead.
Remove env->feature, riscv_feature() and riscv_set_feature(). We also need to bump vmstate_riscv_cpu version_id and minimal_version_id since 'features' is no longer being migrated.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-11-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
|
#
3fe40ef5 |
| 22-Feb-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: remove RISCV_FEATURE_PMP
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarb
target/riscv: remove RISCV_FEATURE_PMP
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
|
#
cdfb2905 |
| 22-Feb-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: remove RISCV_FEATURE_DEBUG
RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ven
target/riscv: remove RISCV_FEATURE_DEBUG
RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
|
#
1e2de2b8 |
| 22-Feb-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv/cpu: remove CPUArchState::features and friends
The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead.
Remove env->feature
target/riscv/cpu: remove CPUArchState::features and friends
The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead.
Remove env->feature, riscv_feature() and riscv_set_feature(). We also need to bump vmstate_riscv_cpu version_id and minimal_version_id since 'features' is no longer being migrated.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-11-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
|
#
3fe40ef5 |
| 22-Feb-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: remove RISCV_FEATURE_PMP
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarb
target/riscv: remove RISCV_FEATURE_PMP
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
|
#
cdfb2905 |
| 22-Feb-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: remove RISCV_FEATURE_DEBUG
RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ven
target/riscv: remove RISCV_FEATURE_DEBUG
RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
|
#
1e2de2b8 |
| 22-Feb-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv/cpu: remove CPUArchState::features and friends
The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead.
Remove env->feature
target/riscv/cpu: remove CPUArchState::features and friends
The attribute is no longer used since we can retrieve all the enabled features in the hart by using cpu->cfg instead.
Remove env->feature, riscv_feature() and riscv_set_feature(). We also need to bump vmstate_riscv_cpu version_id and minimal_version_id since 'features' is no longer being migrated.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-11-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
|
#
3fe40ef5 |
| 22-Feb-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: remove RISCV_FEATURE_PMP
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarb
target/riscv: remove RISCV_FEATURE_PMP
RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-8-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
show more ...
|