Revision tags: v8.1.2 |
|
#
fb80f333 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: move KVM only files to kvm subdir
Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disa
target/riscv: move KVM only files to kvm subdir
Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disable-tcg.
Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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#
5c67bc73 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: remove kvm-stub.c
This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enab
target/riscv: remove kvm-stub.c
This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out in non-KVM builds.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
9c5180d7 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: introduce TCG AccelCPUClass
target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to
target/riscv: introduce TCG AccelCPUClass
target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to a lot of "if tcg" and "if kvm" throughout the code, which isn't wrong, but can get cluttered over time. Splitting acceleration specific code from cpu.c to its own file will help to declutter the existing code and it will also make it easier to support KVM/TCG only builds in the future.
We'll start by adding a new subdir called 'tcg' and a new file called 'tcg-cpu.c'. This file will be used to introduce a new accelerator class for TCG acceleration in RISC-V, allowing us to center all TCG exclusive code in its file instead of using 'cpu.c' for everything. This design is inpired by the work Claudio Fontana did in x86 a few years ago in commit f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using AccelCPUClass").
To avoid moving too much code at once we'll start by adding the new file and TCG AccelCPUClass declaration. The 'class_init' from the accel class will init 'tcg_ops', relieving the common riscv_cpu_class_init() from doing it.
'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having to deal with moving code and files around right now. We'll focus on decoupling the realize() logic first.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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Revision tags: v8.1.2 |
|
#
fb80f333 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: move KVM only files to kvm subdir
Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disa
target/riscv: move KVM only files to kvm subdir
Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disable-tcg.
Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
5c67bc73 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: remove kvm-stub.c
This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enab
target/riscv: remove kvm-stub.c
This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out in non-KVM builds.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
9c5180d7 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: introduce TCG AccelCPUClass
target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to
target/riscv: introduce TCG AccelCPUClass
target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to a lot of "if tcg" and "if kvm" throughout the code, which isn't wrong, but can get cluttered over time. Splitting acceleration specific code from cpu.c to its own file will help to declutter the existing code and it will also make it easier to support KVM/TCG only builds in the future.
We'll start by adding a new subdir called 'tcg' and a new file called 'tcg-cpu.c'. This file will be used to introduce a new accelerator class for TCG acceleration in RISC-V, allowing us to center all TCG exclusive code in its file instead of using 'cpu.c' for everything. This design is inpired by the work Claudio Fontana did in x86 a few years ago in commit f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using AccelCPUClass").
To avoid moving too much code at once we'll start by adding the new file and TCG AccelCPUClass declaration. The 'class_init' from the accel class will init 'tcg_ops', relieving the common riscv_cpu_class_init() from doing it.
'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having to deal with moving code and files around right now. We'll focus on decoupling the realize() logic first.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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Revision tags: v8.1.2 |
|
#
fb80f333 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: move KVM only files to kvm subdir
Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disa
target/riscv: move KVM only files to kvm subdir
Move the files to a 'kvm' dir to promote more code separation between accelerators and making our lives easier supporting build options such as --disable-tcg.
Rename kvm.c to kvm-cpu.c to keep it in line with its TCG counterpart.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-13-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
5c67bc73 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: remove kvm-stub.c
This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enab
target/riscv: remove kvm-stub.c
This file is not needed for some time now. Both kvm_riscv_reset_vcpu() and kvm_riscv_set_irq() have public declarations in kvm_riscv.h and are wrapped in 'if kvm_enabled()' blocks that the compiler will rip it out in non-KVM builds.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-11-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
9c5180d7 |
| 25-Sep-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: introduce TCG AccelCPUClass
target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to
target/riscv: introduce TCG AccelCPUClass
target/riscv/cpu.c needs to handle all possible accelerators (TCG and KVM at this moment) during both init() and realize() time. This forces us to resort to a lot of "if tcg" and "if kvm" throughout the code, which isn't wrong, but can get cluttered over time. Splitting acceleration specific code from cpu.c to its own file will help to declutter the existing code and it will also make it easier to support KVM/TCG only builds in the future.
We'll start by adding a new subdir called 'tcg' and a new file called 'tcg-cpu.c'. This file will be used to introduce a new accelerator class for TCG acceleration in RISC-V, allowing us to center all TCG exclusive code in its file instead of using 'cpu.c' for everything. This design is inpired by the work Claudio Fontana did in x86 a few years ago in commit f5cc5a5c1 ("i386: split cpu accelerators from cpu.c, using AccelCPUClass").
To avoid moving too much code at once we'll start by adding the new file and TCG AccelCPUClass declaration. The 'class_init' from the accel class will init 'tcg_ops', relieving the common riscv_cpu_class_init() from doing it.
'riscv_tcg_ops' is being exported from 'cpu.c' for now to avoid having to deal with moving code and files around right now. We'll focus on decoupling the realize() logic first.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
01c85e60 |
| 04-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
meson: Rename target_softmmu_arch -> target_system_arch
Finish the convertion started with commit de6cd7599b ("meson: Replace softmmu_ss -> system_ss"). If the $target_type is 'system', then use the
meson: Rename target_softmmu_arch -> target_system_arch
Finish the convertion started with commit de6cd7599b ("meson: Replace softmmu_ss -> system_ss"). If the $target_type is 'system', then use the target_system_arch[] source set :)
Mechanical change doing:
$ sed -i -e s/target_softmmu_arch/target_system_arch/g \ $(git grep -l target_softmmu_arch)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-13-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
show more ...
|
#
01c85e60 |
| 04-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
meson: Rename target_softmmu_arch -> target_system_arch
Finish the convertion started with commit de6cd7599b ("meson: Replace softmmu_ss -> system_ss"). If the $target_type is 'system', then use the
meson: Rename target_softmmu_arch -> target_system_arch
Finish the convertion started with commit de6cd7599b ("meson: Replace softmmu_ss -> system_ss"). If the $target_type is 'system', then use the target_system_arch[] source set :)
Mechanical change doing:
$ sed -i -e s/target_softmmu_arch/target_system_arch/g \ $(git grep -l target_softmmu_arch)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004090629.37473-13-philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Revision tags: v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0 |
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#
e13c7d3b |
| 11-Jul-2023 |
Lawrence Hunter <lawrence.hunter@codethink.co.uk> |
target/riscv: Add Zvbc ISA extension support
This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions:
* vclmulh.[vx,vv] * vclmul.[vx,vv]
Transla
target/riscv: Add Zvbc ISA extension support
This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions:
* vclmulh.[vx,vv] * vclmul.[vx,vv]
Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: Max Chou <max.chou@sifive.com> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> [max.chou@sifive.com: Exposed x-zvbc property] Message-ID: <20230711165917.2629866-5-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
98f40dd2 |
| 11-Jul-2023 |
Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> |
target/riscv: Refactor some of the generic vector functionality
Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be use
target/riscv: Refactor some of the generic vector functionality
Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230711165917.2629866-2-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.1.1, v7.2.6, v8.0.5, v8.1.0, v8.1.0-rc4, v8.1.0-rc3, v7.2.5, v8.0.4, v8.1.0-rc2, v8.1.0-rc1, v8.1.0-rc0 |
|
#
e13c7d3b |
| 11-Jul-2023 |
Lawrence Hunter <lawrence.hunter@codethink.co.uk> |
target/riscv: Add Zvbc ISA extension support
This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions:
* vclmulh.[vx,vv] * vclmul.[vx,vv]
Transla
target/riscv: Add Zvbc ISA extension support
This commit adds support for the Zvbc vector-crypto extension, which consists of the following instructions:
* vclmulh.[vx,vv] * vclmul.[vx,vv]
Translation functions are defined in `target/riscv/insn_trans/trans_rvvk.c.inc` and helpers are defined in `target/riscv/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Co-authored-by: Max Chou <max.chou@sifive.com> Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk> Signed-off-by: Lawrence Hunter <lawrence.hunter@codethink.co.uk> Signed-off-by: Max Chou <max.chou@sifive.com> [max.chou@sifive.com: Exposed x-zvbc property] Message-ID: <20230711165917.2629866-5-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
|
#
98f40dd2 |
| 11-Jul-2023 |
Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> |
target/riscv: Refactor some of the generic vector functionality
Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be use
target/riscv: Refactor some of the generic vector functionality
Take some functions/macros out of `vector_helper` and put them in a new module called `vector_internals`. This ensures they can be used by both vector and vector-crypto helpers (latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230711165917.2629866-2-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.3, v7.2.4 |
|
#
de6cd759 |
| 13-Jun-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
meson: Replace softmmu_ss -> system_ss
We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[
meson: Replace softmmu_ss -> system_ss
We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation.
Mechanical change doing:
$ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss)
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4 |
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#
c0177f91 |
| 11-Apr-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: add query-cpy-definitions support
This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more in
target/riscv: add query-cpy-definitions support
This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more information about each CPU.
This initial support includes only the name of the CPU and its typename. Here's what the command produces for the riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false, "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "deprecated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false, "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false, "deprecated": false}] }
Next patch will introduce a way to tell whether a given CPU is static or not.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230411183511.189632-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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|
Revision tags: v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
|
#
ce3af0bb |
| 07-Mar-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.2, v8.0.1, v7.2.3, v7.2.2, v8.0.0, v8.0.0-rc4 |
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#
c0177f91 |
| 11-Apr-2023 |
Daniel Henrique Barboza <dbarboza@ventanamicro.com> |
target/riscv: add query-cpy-definitions support
This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more in
target/riscv: add query-cpy-definitions support
This command is used by tooling like libvirt to retrieve a list of supported CPUs. Each entry returns a CpuDefinitionInfo object that contains more information about each CPU.
This initial support includes only the name of the CPU and its typename. Here's what the command produces for the riscv64 target:
$ ./build/qemu-system-riscv64 -S -M virt -display none -qmp stdio {"QMP": {"version": (...)} {"execute": "qmp_capabilities", "arguments": {"enable": ["oob"]}} {"return": {}} {"execute": "query-cpu-definitions"} {"return": [ {"name": "rv64", "typename": "rv64-riscv-cpu", "static": false, "deprecated": false}, {"name": "sifive-e51", "typename": "sifive-e51-riscv-cpu", "static": false, "deprecated": false}, {"name": "any", "typename": "any-riscv-cpu", "static": false, "deprecated": false}, {"name": "x-rv128", "typename": "x-rv128-riscv-cpu", "static": false, "deprecated": false}, {"name": "shakti-c", "typename": "shakti-c-riscv-cpu", "static": false, "deprecated": false}, {"name": "thead-c906", "typename": "thead-c906-riscv-cpu", "static": false, "deprecated": false}, {"name": "sifive-u54", "typename": "sifive-u54-riscv-cpu", "static": false, "deprecated": false}] }
Next patch will introduce a way to tell whether a given CPU is static or not.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230411183511.189632-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
ce3af0bb |
| 07-Mar-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
target/riscv: add support for Zcmt extension
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
49a7f3aa |
| 31-Jan-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
RISC-V: Adding XTheadCmo ISA extension
This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific
RISC-V: Adding XTheadCmo ISA extension
This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific files. Future patches should be able to easily add additional T-Head extension.
The implementation does not have much functionality (besides accepting the instructions and not qualifying them as illegal instructions if the hart executes in the required privilege level for the instruction), as QEMU does not model CPU caches and instructions are documented to not raise any exceptions.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
49a7f3aa |
| 31-Jan-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
RISC-V: Adding XTheadCmo ISA extension
This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific
RISC-V: Adding XTheadCmo ISA extension
This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific files. Future patches should be able to easily add additional T-Head extension.
The implementation does not have much functionality (besides accepting the instructions and not qualifying them as illegal instructions if the hart executes in the required privilege level for the instruction), as QEMU does not model CPU caches and instructions are documented to not raise any exceptions.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4 |
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#
43888c2f |
| 24-Aug-2022 |
Atish Patra <atishp@rivosinc.com> |
target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified
target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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Revision tags: v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4 |
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#
43888c2f |
| 24-Aug-2022 |
Atish Patra <atishp@rivosinc.com> |
target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified
target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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Revision tags: v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4 |
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#
43888c2f |
| 24-Aug-2022 |
Atish Patra <atishp@rivosinc.com> |
target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified
target/riscv: Add stimecmp support
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
show more ...
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