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0d57cd61 |
| 19-May-2023 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (tests/tcg/hexagon) Clean up Hexagon check-tcg tests
Move test infra to header file check functions (always print line number on error) USR manipulation Useful floating point val
Hexagon (tests/tcg/hexagon) Clean up Hexagon check-tcg tests
Move test infra to header file check functions (always print line number on error) USR manipulation Useful floating point values Use stdint.h types Use stdbool.h bool where appropriate Use trip counts local to for loop
Suggested-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Tested-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230522174341.1805460-1-tsimpson@quicinc.com>
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#
0d57cd61 |
| 19-May-2023 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (tests/tcg/hexagon) Clean up Hexagon check-tcg tests
Move test infra to header file check functions (always print line number on error) USR manipulation Useful floating point val
Hexagon (tests/tcg/hexagon) Clean up Hexagon check-tcg tests
Move test infra to header file check functions (always print line number on error) USR manipulation Useful floating point values Use stdint.h types Use stdbool.h bool where appropriate Use trip counts local to for loop
Suggested-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Tested-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230522174341.1805460-1-tsimpson@quicinc.com>
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Revision tags: v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
eaee3b6f |
| 29-Dec-2022 |
Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> |
tests/tcg/hexagon: fix underspecifed asm constraints
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail.
In misc.c, the 'result' output needs th
tests/tcg/hexagon: fix underspecifed asm constraints
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail.
In misc.c, the 'result' output needs the early clobber modifier since the rest of the inputs are read after assignment to the output register.
In mem_noshuf.c, the register r7 is written to but not specified in the clobber list.
Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229081836.12130-1-quic_mthiyaga@quicinc.com>
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Revision tags: v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
eaee3b6f |
| 29-Dec-2022 |
Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> |
tests/tcg/hexagon: fix underspecifed asm constraints
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail.
In misc.c, the 'result' output needs th
tests/tcg/hexagon: fix underspecifed asm constraints
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail.
In misc.c, the 'result' output needs the early clobber modifier since the rest of the inputs are read after assignment to the output register.
In mem_noshuf.c, the register r7 is written to but not specified in the clobber list.
Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229081836.12130-1-quic_mthiyaga@quicinc.com>
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Revision tags: v7.2.2, v8.0.0, v8.0.0-rc4, v8.0.0-rc3, v7.2.1, v8.0.0-rc2, v8.0.0-rc1, v8.0.0-rc0 |
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#
eaee3b6f |
| 29-Dec-2022 |
Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> |
tests/tcg/hexagon: fix underspecifed asm constraints
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail.
In misc.c, the 'result' output needs th
tests/tcg/hexagon: fix underspecifed asm constraints
There are two test cases where the inline asm doesn't have the correct constraints causing them to fail.
In misc.c, the 'result' output needs the early clobber modifier since the rest of the inputs are read after assignment to the output register.
In mem_noshuf.c, the register r7 is written to but not specified in the clobber list.
Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221229081836.12130-1-quic_mthiyaga@quicinc.com>
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Revision tags: v7.2.0, v7.2.0-rc4, v7.2.0-rc3, v7.2.0-rc2, v7.2.0-rc1, v7.2.0-rc0, v7.1.0, v7.1.0-rc4, v7.1.0-rc3, v7.1.0-rc2, v7.1.0-rc1, v7.1.0-rc0 |
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#
cab86dea |
| 07-Jul-2022 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (target/hexagon) fix store w/mem_noshuf & predicated load
Call the CHECK_NOSHUF macro multiple times: once in the fGEN_TCG_PRED_LOAD() and again in fLOAD().
Before this commit, a packet wit
Hexagon (target/hexagon) fix store w/mem_noshuf & predicated load
Call the CHECK_NOSHUF macro multiple times: once in the fGEN_TCG_PRED_LOAD() and again in fLOAD().
Before this commit, a packet with a store and a predicated load with mem_noshuf that gets encoded like this:
{ P0 = cmp.eq(R17,#0x0) memw(R18+#0x0) = R2 if (!P0.new) R3 = memw(R17+#0x4) }
... would end up generating a branch over both the load and the store like so:
... brcond_i32 loc17,$0x0,eq,$L1 mov_i32 loc18,store_addr_1 qemu_st_i32 store_val32_1,store_addr_1,leul,0 qemu_ld_i32 loc16,loc7,leul,0 set_label $L1 ...
Test cases added to tests/tcg/hexagon/mem_noshuf.c
Co-authored-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220707210546.15985-2-tsimpson@quicinc.com>
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Revision tags: v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0, v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1, v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0, v6.0.0, v6.0.0-rc5, v6.0.0-rc4, v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1, v6.0.0-rc0 |
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#
825d6eba |
| 08-Feb-2021 |
Taylor Simpson <tsimpson@quicinc.com> |
Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-33-git-send-email-tsimpson@quicinc.com> Signed-off-
Hexagon (tests/tcg/hexagon) TCG tests - atomics/load/store/misc
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <1612763186-18161-33-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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