Lines Matching defs:tmp
30 OP(080) { int tmp; BRA(1); } OPEND(); // 4 BRA REL variable
31 OP(0a0) { int tmp; CYCTOCK(2); RD_IMM; LDY; } OPEND(); // 2 LDY IMM variable
32 OP(0c0) { int tmp; CYCTOCK(2); RD_IMM; CPY; } OPEND(); // 2 CPY IMM variable
33 OP(0e0) { int tmp; CYCTOCK(2); RD_IMM; CPX; } OPEND(); // 2 CPX IMM variable
35 OP(010) { int tmp; BPL; } OPEND(); // 2/4 BPL REL variable
36 OP(030) { int tmp; BMI; } OPEND(); // 2/4 BMI REL variable
37 OP(050) { int tmp; BVC; } OPEND(); // 2/4 BVC REL variable
38 OP(070) { int tmp; BVS; } OPEND(); // 2/4 BVS REL variable
39 OP(090) { int tmp; BCC; } OPEND(); // 2/4 BCC REL variable
40 OP(0b0) { int tmp; BCS; } OPEND(); // 2/4 BCS REL variable
41 OP(0d0) { int tmp; BNE; } OPEND(); // 2/4 BNE REL variable
42 OP(0f0) { int tmp; BEQ; } OPEND(); // 2/4 BEQ REL variable
44 OP(001) { int tmp; CYCTOCK(7); RD_IDX; ORA; } OPEND(); // 7 ORA IDX variable
45 OP(021) { int tmp; CYCTOCK(7); RD_IDX; AND; } OPEND(); // 7 AND IDX variable
46 OP(041) { int tmp; CYCTOCK(7); RD_IDX; EOR; } OPEND(); // 7 EOR IDX variable
47 OP(061) { int tmp; CYCTOCK(7); RD_IDX; ADC; } OPEND(); // 7 ADC IDX variable
48 OP(081) { int tmp; CYCTOCK(7); STA; WR_IDX; } OPEND(); // 7 STA IDX variable
49 OP(0a1) { int tmp; CYCTOCK(7); RD_IDX; LDA; } OPEND(); // 7 LDA IDX variable
50 OP(0c1) { int tmp; CYCTOCK(7); RD_IDX; CMP; } OPEND(); // 7 CMP IDX variable
51 OP(0e1) { int tmp; CYCTOCK(7); RD_IDX; SBC; } OPEND(); // 7 SBC IDX variable
53 OP(011) { int tmp; CYCTOCK(7); RD_IDY; ORA; } OPEND(); // 7 ORA IDY variable
54 OP(031) { int tmp; CYCTOCK(7); RD_IDY; AND; } OPEND(); // 7 AND IDY variable
55 OP(051) { int tmp; CYCTOCK(7); RD_IDY; EOR; } OPEND(); // 7 EOR IDY variable
56 OP(071) { int tmp; CYCTOCK(7); RD_IDY; ADC; } OPEND(); // 7 ADC AZP variable
57 OP(091) { int tmp; CYCTOCK(7); STA; WR_IDY; } OPEND(); // 7 STA IDY variable
58 OP(0b1) { int tmp; CYCTOCK(7); RD_IDY; LDA; } OPEND(); // 7 LDA IDY variable
59 OP(0d1) { int tmp; CYCTOCK(7); RD_IDY; CMP; } OPEND(); // 7 CMP IDY variable
60 OP(0f1) { int tmp; CYCTOCK(7); RD_IDY; SBC; } OPEND(); // 7 SBC IDY variable
62 OP(002) { int tmp; CYCTOCK(3); SXY; } OPEND(); // 3 SXY variable
63 OP(022) { int tmp; CYCTOCK(3); SAX; } OPEND(); // 3 SAX variable
64 OP(042) { int tmp; CYCTOCK(3); SAY; } OPEND(); // 3 SAY variable
67 OP(0a2) { int tmp; CYCTOCK(2); RD_IMM; LDX; } OPEND(); // 2 LDX IMM variable
71 OP(012) { int tmp; CYCTOCK(7); RD_ZPI; ORA; } OPEND(); // 7 ORA ZPI variable
72 OP(032) { int tmp; CYCTOCK(7); RD_ZPI; AND; } OPEND(); // 7 AND ZPI variable
73 OP(052) { int tmp; CYCTOCK(7); RD_ZPI; EOR; } OPEND(); // 7 EOR ZPI variable
74 OP(072) { int tmp; CYCTOCK(7); RD_ZPI; ADC; } OPEND(); // 7 ADC ZPI variable
75 OP(092) { int tmp; CYCTOCK(7); STA; WR_ZPI; } OPEND(); // 7 STA ZPI variable
76 OP(0b2) { int tmp; CYCTOCK(7); RD_ZPI; LDA; } OPEND(); // 7 LDA ZPI variable
77 OP(0d2) { int tmp; CYCTOCK(7); RD_ZPI; CMP; } OPEND(); // 7 CMP ZPI variable
78 OP(0f2) { int tmp; CYCTOCK(7); RD_ZPI; SBC; } OPEND(); // 7 SBC ZPI variable
80 OP(003) { int tmp; CYCTOCK(4); RD_IMM; ST0; } OPEND(); // 4 ST0 IMM variable
81 OP(023) { int tmp; CYCTOCK(4); RD_IMM; ST2; } OPEND(); // 4 ST2 IMM variable
82 OP(043) { int tmp; CYCTOCK(4); RD_IMM; TMA; } OPEND(); // 4 TMA variable
84 OP(083) { int tmp,tmp2; CYCTOCK(7); RD_IMM2; RD_ZPG; TST; WB_EAZ;} OPEND(); // 7 TST IMM,ZPG variable
85 OP(0a3) { int tmp,tmp2; CYCTOCK(7); RD_IMM2; RD_ZPX; TST; WB_EAZ;} OPEND(); // 7 TST IMM,ZPX variable
89 OP(013) { int tmp; CYCTOCK(4); RD_IMM; ST1; } OPEND(); // 4 ST1 variable
91 OP(053) { int tmp; CYCTOCK(5); RD_IMM; TAM; } OPEND(); // 5 TAM IMM variable
93 OP(093) { int tmp,tmp2; CYCTOCK(8); RD_IMM2; RD_ABS; TST; WB_EA;} OPEND(); // 8 TST IMM,ABS variable
94 OP(0b3) { int tmp,tmp2; CYCTOCK(8); RD_IMM2; RD_ABX; TST; WB_EA;} OPEND(); // 8 TST IMM,ABX variable
98 OP(004) { int tmp; CYCTOCK(6); RD_ZPG; TSB; WB_EAZ; } OPEND(); // 6 TSB ZPG variable
99 OP(024) { int tmp; CYCTOCK(4); RD_ZPG; BIT; } OPEND(); // 4 BIT ZPG variable
100 OP(044) { int tmp; BSR; } OPEND(); // 8 BSR REL variable
101 OP(064) { int tmp; CYCTOCK(4); STZ; WR_ZPG; } OPEND(); // 4 STZ ZPG variable
102 OP(084) { int tmp; CYCTOCK(4); STY; WR_ZPG; } OPEND(); // 4 STY ZPG variable
103 OP(0a4) { int tmp; CYCTOCK(4); RD_ZPG; LDY; } OPEND(); // 4 LDY ZPG variable
104 OP(0c4) { int tmp; CYCTOCK(4); RD_ZPG; CPY; } OPEND(); // 4 CPY ZPG variable
105 OP(0e4) { int tmp; CYCTOCK(4); RD_ZPG; CPX; } OPEND(); // 4 CPX ZPG variable
107 OP(014) { int tmp; CYCTOCK(6); RD_ZPG; TRB; WB_EAZ; } OPEND(); // 6 TRB ZPG variable
108 OP(034) { int tmp; CYCTOCK(4); RD_ZPX; BIT; } OPEND(); // 4 BIT ZPX variable
110 OP(074) { int tmp; CYCTOCK(4); STZ; WR_ZPX; } OPEND(); // 4 STZ ZPX variable
111 OP(094) { int tmp; CYCTOCK(4); STY; WR_ZPX; } OPEND(); // 4 STY ZPX variable
112 OP(0b4) { int tmp; CYCTOCK(4); RD_ZPX; LDY; } OPEND(); // 4 LDY ZPX variable
116 OP(005) { int tmp; CYCTOCK(4); RD_ZPG; ORA; } OPEND(); // 4 ORA ZPG variable
117 OP(025) { int tmp; CYCTOCK(4); RD_ZPG; AND; } OPEND(); // 4 AND ZPG variable
118 OP(045) { int tmp; CYCTOCK(4); RD_ZPG; EOR; } OPEND(); // 4 EOR ZPG variable
119 OP(065) { int tmp; CYCTOCK(4); RD_ZPG; ADC; } OPEND(); // 4 ADC ZPG variable
120 OP(085) { int tmp; CYCTOCK(4); STA; WR_ZPG; } OPEND(); // 4 STA ZPG variable
121 OP(0a5) { int tmp; CYCTOCK(4); RD_ZPG; LDA; } OPEND(); // 4 LDA ZPG variable
122 OP(0c5) { int tmp; CYCTOCK(4); RD_ZPG; CMP; } OPEND(); // 4 CMP ZPG variable
123 OP(0e5) { int tmp; CYCTOCK(4); RD_ZPG; SBC; } OPEND(); // 4 SBC ZPG variable
125 OP(015) { int tmp; CYCTOCK(4); RD_ZPX; ORA; } OPEND(); // 4 ORA ZPX variable
126 OP(035) { int tmp; CYCTOCK(4); RD_ZPX; AND; } OPEND(); // 4 AND ZPX variable
127 OP(055) { int tmp; CYCTOCK(4); RD_ZPX; EOR; } OPEND(); // 4 EOR ZPX variable
128 OP(075) { int tmp; CYCTOCK(4); RD_ZPX; ADC; } OPEND(); // 4 ADC ZPX variable
129 OP(095) { int tmp; CYCTOCK(4); STA; WR_ZPX; } OPEND(); // 4 STA ZPX variable
130 OP(0b5) { int tmp; CYCTOCK(4); RD_ZPX; LDA; } OPEND(); // 4 LDA ZPX variable
131 OP(0d5) { int tmp; CYCTOCK(4); RD_ZPX; CMP; } OPEND(); // 4 CMP ZPX variable
132 OP(0f5) { int tmp; CYCTOCK(4); RD_ZPX; SBC; } OPEND(); // 4 SBC ZPX variable
134 OP(006) { int tmp; CYCTOCK(6); RD_ZPG; ASL; WB_EAZ; } OPEND(); // 6 ASL ZPG variable
135 OP(026) { int tmp; CYCTOCK(6); RD_ZPG; ROL; WB_EAZ; } OPEND(); // 6 ROL ZPG variable
136 OP(046) { int tmp; CYCTOCK(6); RD_ZPG; LSR; WB_EAZ; } OPEND(); // 6 LSR ZPG variable
137 OP(066) { int tmp; CYCTOCK(6); RD_ZPG; ROR; WB_EAZ; } OPEND(); // 6 ROR ZPG variable
138 OP(086) { int tmp; CYCTOCK(4); STX; WR_ZPG; } OPEND(); // 4 STX ZPG variable
139 OP(0a6) { int tmp; CYCTOCK(4); RD_ZPG; LDX; } OPEND(); // 4 LDX ZPG variable
140 OP(0c6) { int tmp; CYCTOCK(6); RD_ZPG; DEC; WB_EAZ; } OPEND(); // 6 DEC ZPG variable
141 OP(0e6) { int tmp; CYCTOCK(6); RD_ZPG; INC; WB_EAZ; } OPEND(); // 6 INC ZPG variable
143 OP(016) { int tmp; CYCTOCK(6); RD_ZPX; ASL; WB_EAZ } OPEND(); // 6 ASL ZPX variable
144 OP(036) { int tmp; CYCTOCK(6); RD_ZPX; ROL; WB_EAZ } OPEND(); // 6 ROL ZPX variable
145 OP(056) { int tmp; CYCTOCK(6); RD_ZPX; LSR; WB_EAZ } OPEND(); // 6 LSR ZPX variable
146 OP(076) { int tmp; CYCTOCK(6); RD_ZPX; ROR; WB_EAZ } OPEND(); // 6 ROR ZPX variable
147 OP(096) { int tmp; CYCTOCK(4); STX; WR_ZPY; } OPEND(); // 4 STX ZPY variable
148 OP(0b6) { int tmp; CYCTOCK(4); RD_ZPY; LDX; } OPEND(); // 4 LDX ZPY variable
149 OP(0d6) { int tmp; CYCTOCK(6); RD_ZPX; DEC; WB_EAZ; } OPEND(); // 6 DEC ZPX variable
150 OP(0f6) { int tmp; CYCTOCK(6); RD_ZPX; INC; WB_EAZ; } OPEND(); // 6 INC ZPX variable
152 OP(007) { int tmp; CYCTOCK(7); RD_ZPG; RMB(0);WB_EAZ;} OPEND(); // 7 RMB0 ZPG variable
153 OP(027) { int tmp; CYCTOCK(7); RD_ZPG; RMB(2);WB_EAZ;} OPEND(); // 7 RMB2 ZPG variable
154 OP(047) { int tmp; CYCTOCK(7); RD_ZPG; RMB(4);WB_EAZ;} OPEND(); // 7 RMB4 ZPG variable
155 OP(067) { int tmp; CYCTOCK(7); RD_ZPG; RMB(6);WB_EAZ;} OPEND(); // 7 RMB6 ZPG variable
156 OP(087) { int tmp; CYCTOCK(7); RD_ZPG; SMB(0);WB_EAZ;} OPEND(); // 7 SMB0 ZPG variable
157 OP(0a7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(2);WB_EAZ;} OPEND(); // 7 SMB2 ZPG variable
158 OP(0c7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(4);WB_EAZ;} OPEND(); // 7 SMB4 ZPG variable
159 OP(0e7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(6);WB_EAZ;} OPEND(); // 7 SMB6 ZPG variable
161 OP(017) { int tmp; CYCTOCK(7); RD_ZPG; RMB(1);WB_EAZ;} OPEND(); // 7 RMB1 ZPG variable
162 OP(037) { int tmp; CYCTOCK(7); RD_ZPG; RMB(3);WB_EAZ;} OPEND(); // 7 RMB3 ZPG variable
163 OP(057) { int tmp; CYCTOCK(7); RD_ZPG; RMB(5);WB_EAZ;} OPEND(); // 7 RMB5 ZPG variable
164 OP(077) { int tmp; CYCTOCK(7); RD_ZPG; RMB(7);WB_EAZ;} OPEND(); // 7 RMB7 ZPG variable
165 OP(097) { int tmp; CYCTOCK(7); RD_ZPG; SMB(1);WB_EAZ;} OPEND(); // 7 SMB1 ZPG variable
166 OP(0b7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(3);WB_EAZ;} OPEND(); // 7 SMB3 ZPG variable
167 OP(0d7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(5);WB_EAZ;} OPEND(); // 7 SMB5 ZPG variable
168 OP(0f7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(7);WB_EAZ;} OPEND(); // 7 SMB7 ZPG variable
188 OP(009) { int tmp; CYCTOCK(2); RD_IMM; ORA; } OPEND(); // 2 ORA IMM variable
189 OP(029) { int tmp; CYCTOCK(2); RD_IMM; AND; } OPEND(); // 2 AND IMM variable
190 OP(049) { int tmp; CYCTOCK(2); RD_IMM; EOR; } OPEND(); // 2 EOR IMM variable
191 OP(069) { int tmp; CYCTOCK(2); RD_IMM; ADC; } OPEND(); // 2 ADC IMM variable
192 OP(089) { int tmp; CYCTOCK(2); RD_IMM; BIT; } OPEND(); // 2 BIT IMM variable
193 OP(0a9) { int tmp; CYCTOCK(2); RD_IMM; LDA; } OPEND(); // 2 LDA IMM variable
194 OP(0c9) { int tmp; CYCTOCK(2); RD_IMM; CMP; } OPEND(); // 2 CMP IMM variable
195 OP(0e9) { int tmp; CYCTOCK(2); RD_IMM; SBC; } OPEND(); // 2 SBC IMM variable
197 OP(019) { int tmp; CYCTOCK(5); RD_ABY; ORA; } OPEND(); // 5 ORA ABY variable
198 OP(039) { int tmp; CYCTOCK(5); RD_ABY; AND; } OPEND(); // 5 AND ABY variable
199 OP(059) { int tmp; CYCTOCK(5); RD_ABY; EOR; } OPEND(); // 5 EOR ABY variable
200 OP(079) { int tmp; CYCTOCK(5); RD_ABY; ADC; } OPEND(); // 5 ADC ABY variable
201 OP(099) { int tmp; CYCTOCK(5); STA; WR_ABY; } OPEND(); // 5 STA ABY variable
202 OP(0b9) { int tmp; CYCTOCK(5); RD_ABY; LDA; } OPEND(); // 5 LDA ABY variable
203 OP(0d9) { int tmp; CYCTOCK(5); RD_ABY; CMP; } OPEND(); // 5 CMP ABY variable
204 OP(0f9) { int tmp; CYCTOCK(5); RD_ABY; SBC; } OPEND(); // 5 SBC ABY variable
206 OP(00a) { int tmp; CYCTOCK(2); RD_ACC; ASL; WB_ACC; } OPEND(); // 2 ASL A variable
207 OP(02a) { int tmp; CYCTOCK(2); RD_ACC; ROL; WB_ACC; } OPEND(); // 2 ROL A variable
208 OP(04a) { int tmp; CYCTOCK(2); RD_ACC; LSR; WB_ACC; } OPEND(); // 2 LSR A variable
209 OP(06a) { int tmp; CYCTOCK(2); RD_ACC; ROR; WB_ACC; } OPEND(); // 2 ROR A variable
242 OP(00c) { int tmp; CYCTOCK(7); RD_ABS; TSB; WB_EA; } OPEND(); // 7 TSB ABS variable
243 OP(02c) { int tmp; CYCTOCK(5); RD_ABS; BIT; } OPEND(); // 5 BIT ABS variable
245 OP(06c) { int tmp; CYCTOCK(7); EA_IND; JMP; } OPEND(); // 7 JMP IND variable
246 OP(08c) { int tmp; CYCTOCK(5); STY; WR_ABS; } OPEND(); // 5 STY ABS variable
247 OP(0ac) { int tmp; CYCTOCK(5); RD_ABS; LDY; } OPEND(); // 5 LDY ABS variable
248 OP(0cc) { int tmp; CYCTOCK(5); RD_ABS; CPY; } OPEND(); // 5 CPY ABS variable
249 OP(0ec) { int tmp; CYCTOCK(5); RD_ABS; CPX; } OPEND(); // 5 CPX ABS variable
251 OP(01c) { int tmp; CYCTOCK(7); RD_ABS; TRB; WB_EA; } OPEND(); // 7 TRB ABS variable
252 OP(03c) { int tmp; CYCTOCK(5); RD_ABX; BIT; } OPEND(); // 5 BIT ABX variable
254 OP(07c) { int tmp; CYCTOCK(7); EA_IAX; JMP; } OPEND(); // 7 JMP IAX variable
255 OP(09c) { int tmp; CYCTOCK(5); STZ; WR_ABS; } OPEND(); // 5 STZ ABS variable
256 OP(0bc) { int tmp; CYCTOCK(5); RD_ABX; LDY; } OPEND(); // 5 LDY ABX variable
261 OP(00d) { int tmp; CYCTOCK(5); RD_ABS; ORA; } OPEND(); // 5 ORA ABS variable
262 OP(02d) { int tmp; CYCTOCK(5); RD_ABS; AND; } OPEND(); // 4 AND ABS variable
263 OP(04d) { int tmp; CYCTOCK(5); RD_ABS; EOR; } OPEND(); // 4 EOR ABS variable
264 OP(06d) { int tmp; CYCTOCK(5); RD_ABS; ADC; } OPEND(); // 4 ADC ABS variable
265 OP(08d) { int tmp; CYCTOCK(5); STA; WR_ABS; } OPEND(); // 4 STA ABS variable
266 OP(0ad) { int tmp; CYCTOCK(5); RD_ABS; LDA; } OPEND(); // 4 LDA ABS variable
267 OP(0cd) { int tmp; CYCTOCK(5); RD_ABS; CMP; } OPEND(); // 4 CMP ABS variable
268 OP(0ed) { int tmp; CYCTOCK(5); RD_ABS; SBC; } OPEND(); // 4 SBC ABS variable
270 OP(01d) { int tmp; CYCTOCK(5); RD_ABX; ORA; } OPEND(); // 5 ORA ABX variable
271 OP(03d) { int tmp; CYCTOCK(5); RD_ABX; AND; } OPEND(); // 4 AND ABX variable
272 OP(05d) { int tmp; CYCTOCK(5); RD_ABX; EOR; } OPEND(); // 4 EOR ABX variable
273 OP(07d) { int tmp; CYCTOCK(5); RD_ABX; ADC; } OPEND(); // 4 ADC ABX variable
274 OP(09d) { int tmp; CYCTOCK(5); STA; WR_ABX; } OPEND(); // 5 STA ABX variable
275 OP(0bd) { int tmp; CYCTOCK(5); RD_ABX; LDA; } OPEND(); // 5 LDA ABX variable
276 OP(0dd) { int tmp; CYCTOCK(5); RD_ABX; CMP; } OPEND(); // 4 CMP ABX variable
277 OP(0fd) { int tmp; CYCTOCK(5); RD_ABX; SBC; } OPEND(); // 4 SBC ABX variable
279 OP(00e) { int tmp; CYCTOCK(7); RD_ABS; ASL; WB_EA; } OPEND(); // 6 ASL ABS variable
280 OP(02e) { int tmp; CYCTOCK(7); RD_ABS; ROL; WB_EA; } OPEND(); // 6 ROL ABS variable
281 OP(04e) { int tmp; CYCTOCK(7); RD_ABS; LSR; WB_EA; } OPEND(); // 6 LSR ABS variable
282 OP(06e) { int tmp; CYCTOCK(7); RD_ABS; ROR; WB_EA; } OPEND(); // 6 ROR ABS variable
283 OP(08e) { int tmp; CYCTOCK(5); STX; WR_ABS; } OPEND(); // 4 STX ABS variable
284 OP(0ae) { int tmp; CYCTOCK(5); RD_ABS; LDX; } OPEND(); // 5 LDX ABS variable
285 OP(0ce) { int tmp; CYCTOCK(7); RD_ABS; DEC; WB_EA; } OPEND(); // 6 DEC ABS variable
286 OP(0ee) { int tmp; CYCTOCK(7); RD_ABS; INC; WB_EA; } OPEND(); // 6 INC ABS variable
288 OP(01e) { int tmp; CYCTOCK(7); RD_ABX; ASL; WB_EA; } OPEND(); // 7 ASL ABX variable
289 OP(03e) { int tmp; CYCTOCK(7); RD_ABX; ROL; WB_EA; } OPEND(); // 7 ROL ABX variable
290 OP(05e) { int tmp; CYCTOCK(7); RD_ABX; LSR; WB_EA; } OPEND(); // 7 LSR ABX variable
291 OP(07e) { int tmp; CYCTOCK(7); RD_ABX; ROR; WB_EA; } OPEND(); // 7 ROR ABX variable
292 OP(09e) { int tmp; CYCTOCK(5); STZ; WR_ABX; } OPEND(); // 5 STZ ABX variable
293 OP(0be) { int tmp; CYCTOCK(5); RD_ABY; LDX; } OPEND(); // 4 LDX ABY variable
294 OP(0de) { int tmp; CYCTOCK(7); RD_ABX; DEC; WB_EA; } OPEND(); // 7 DEC ABX variable
295 OP(0fe) { int tmp; CYCTOCK(7); RD_ABX; INC; WB_EA; } OPEND(); // 7 INC ABX variable
297 OP(00f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(0); } OPEND(); // 6/8 BBR0 ZPG,REL variable
298 OP(02f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(2); } OPEND(); // 6/8 BBR2 ZPG,REL variable
299 OP(04f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(4); } OPEND(); // 6/8 BBR4 ZPG,REL variable
300 OP(06f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(6); } OPEND(); // 6/8 BBR6 ZPG,REL variable
301 OP(08f) { int tmp; CYCTOCK(4); RD_ZPG; BBS(0); } OPEND(); // 6/8 BBS0 ZPG,REL variable
302 OP(0af) { int tmp; CYCTOCK(4); RD_ZPG; BBS(2); } OPEND(); // 6/8 BBS2 ZPG,REL variable
303 OP(0cf) { int tmp; CYCTOCK(4); RD_ZPG; BBS(4); } OPEND(); // 6/8 BBS4 ZPG,REL variable
304 OP(0ef) { int tmp; CYCTOCK(4); RD_ZPG; BBS(6); } OPEND(); // 6/8 BBS6 ZPG,REL variable
306 OP(01f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(1); } OPEND(); // 6/8 BBR1 ZPG,REL variable
307 OP(03f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(3); } OPEND(); // 6/8 BBR3 ZPG,REL variable
308 OP(05f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(5); } OPEND(); // 6/8 BBR5 ZPG,REL variable
309 OP(07f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(7); } OPEND(); // 6/8 BBR7 ZPG,REL variable
310 OP(09f) { int tmp; CYCTOCK(4); RD_ZPG; BBS(1); } OPEND(); // 6/8 BBS1 ZPG,REL variable
311 OP(0bf) { int tmp; CYCTOCK(4); RD_ZPG; BBS(3); } OPEND(); // 6/8 BBS3 ZPG,REL variable
312 OP(0df) { int tmp; CYCTOCK(4); RD_ZPG; BBS(5); } OPEND(); // 6/8 BBS5 ZPG,REL variable
313 OP(0ff) { int tmp; CYCTOCK(4); RD_ZPG; BBS(7); } OPEND(); // 6/8 BBS7 ZPG,REL variable