1 /***************************************************************************** 2 3 tblh6280.c 4 5 Copyright (c) 1999 Bryan McPhail, mish@tendril.co.uk 6 7 This source code is based (with permission!) on the 6502 emulator by 8 Juergen Buchmueller. It is released as part of the Mame emulator project. 9 Let me know if you intend to use this code in any other project. 10 11 ******************************************************************************/ 12 13 14 #undef OP 15 //#define OP(nnn) static __inline__ void h6280_##nnn(h6280_Regs *h6280) 16 #define OP(nnn) case 0x##nnn: 17 #define OPEND() break; 18 19 /***************************************************************************** 20 ***************************************************************************** 21 * 22 * Hu6280 opcodes 23 * 24 ***************************************************************************** 25 * op temp cycles rdmem opc wrmem ******************/ 26 OP(000) { CYCTOCK(8); BRK; } OPEND(); // 8 BRK 27 OP(020) { CYCTOCK(7); EA_ABS; JSR; } OPEND(); // 7 JSR ABS 28 OP(040) { CYCTOCK(7); RTI; } OPEND(); // 7 RTI 29 OP(060) { CYCTOCK(7); RTS; } OPEND(); // 7 RTS 30 OP(080) { int tmp; BRA(1); } OPEND(); // 4 BRA REL 31 OP(0a0) { int tmp; CYCTOCK(2); RD_IMM; LDY; } OPEND(); // 2 LDY IMM 32 OP(0c0) { int tmp; CYCTOCK(2); RD_IMM; CPY; } OPEND(); // 2 CPY IMM 33 OP(0e0) { int tmp; CYCTOCK(2); RD_IMM; CPX; } OPEND(); // 2 CPX IMM 34 35 OP(010) { int tmp; BPL; } OPEND(); // 2/4 BPL REL 36 OP(030) { int tmp; BMI; } OPEND(); // 2/4 BMI REL 37 OP(050) { int tmp; BVC; } OPEND(); // 2/4 BVC REL 38 OP(070) { int tmp; BVS; } OPEND(); // 2/4 BVS REL 39 OP(090) { int tmp; BCC; } OPEND(); // 2/4 BCC REL 40 OP(0b0) { int tmp; BCS; } OPEND(); // 2/4 BCS REL 41 OP(0d0) { int tmp; BNE; } OPEND(); // 2/4 BNE REL 42 OP(0f0) { int tmp; BEQ; } OPEND(); // 2/4 BEQ REL 43 44 OP(001) { int tmp; CYCTOCK(7); RD_IDX; ORA; } OPEND(); // 7 ORA IDX 45 OP(021) { int tmp; CYCTOCK(7); RD_IDX; AND; } OPEND(); // 7 AND IDX 46 OP(041) { int tmp; CYCTOCK(7); RD_IDX; EOR; } OPEND(); // 7 EOR IDX 47 OP(061) { int tmp; CYCTOCK(7); RD_IDX; ADC; } OPEND(); // 7 ADC IDX 48 OP(081) { int tmp; CYCTOCK(7); STA; WR_IDX; } OPEND(); // 7 STA IDX 49 OP(0a1) { int tmp; CYCTOCK(7); RD_IDX; LDA; } OPEND(); // 7 LDA IDX 50 OP(0c1) { int tmp; CYCTOCK(7); RD_IDX; CMP; } OPEND(); // 7 CMP IDX 51 OP(0e1) { int tmp; CYCTOCK(7); RD_IDX; SBC; } OPEND(); // 7 SBC IDX 52 53 OP(011) { int tmp; CYCTOCK(7); RD_IDY; ORA; } OPEND(); // 7 ORA IDY 54 OP(031) { int tmp; CYCTOCK(7); RD_IDY; AND; } OPEND(); // 7 AND IDY 55 OP(051) { int tmp; CYCTOCK(7); RD_IDY; EOR; } OPEND(); // 7 EOR IDY 56 OP(071) { int tmp; CYCTOCK(7); RD_IDY; ADC; } OPEND(); // 7 ADC AZP 57 OP(091) { int tmp; CYCTOCK(7); STA; WR_IDY; } OPEND(); // 7 STA IDY 58 OP(0b1) { int tmp; CYCTOCK(7); RD_IDY; LDA; } OPEND(); // 7 LDA IDY 59 OP(0d1) { int tmp; CYCTOCK(7); RD_IDY; CMP; } OPEND(); // 7 CMP IDY 60 OP(0f1) { int tmp; CYCTOCK(7); RD_IDY; SBC; } OPEND(); // 7 SBC IDY 61 62 OP(002) { int tmp; CYCTOCK(3); SXY; } OPEND(); // 3 SXY 63 OP(022) { int tmp; CYCTOCK(3); SAX; } OPEND(); // 3 SAX 64 OP(042) { int tmp; CYCTOCK(3); SAY; } OPEND(); // 3 SAY 65 OP(062) { CYCTOCK(2); CLA; } OPEND(); // 2 CLA 66 OP(082) { CYCTOCK(2); CLX; } OPEND(); // 2 CLX 67 OP(0a2) { int tmp; CYCTOCK(2); RD_IMM; LDX; } OPEND(); // 2 LDX IMM 68 OP(0c2) { CYCTOCK(2); CLY; } OPEND(); // 2 CLY 69 OP(0e2) { ILL; } OPEND(); // 2 ??? 70 71 OP(012) { int tmp; CYCTOCK(7); RD_ZPI; ORA; } OPEND(); // 7 ORA ZPI 72 OP(032) { int tmp; CYCTOCK(7); RD_ZPI; AND; } OPEND(); // 7 AND ZPI 73 OP(052) { int tmp; CYCTOCK(7); RD_ZPI; EOR; } OPEND(); // 7 EOR ZPI 74 OP(072) { int tmp; CYCTOCK(7); RD_ZPI; ADC; } OPEND(); // 7 ADC ZPI 75 OP(092) { int tmp; CYCTOCK(7); STA; WR_ZPI; } OPEND(); // 7 STA ZPI 76 OP(0b2) { int tmp; CYCTOCK(7); RD_ZPI; LDA; } OPEND(); // 7 LDA ZPI 77 OP(0d2) { int tmp; CYCTOCK(7); RD_ZPI; CMP; } OPEND(); // 7 CMP ZPI 78 OP(0f2) { int tmp; CYCTOCK(7); RD_ZPI; SBC; } OPEND(); // 7 SBC ZPI 79 80 OP(003) { int tmp; CYCTOCK(4); RD_IMM; ST0; } OPEND(); // 4 ST0 IMM 81 OP(023) { int tmp; CYCTOCK(4); RD_IMM; ST2; } OPEND(); // 4 ST2 IMM 82 OP(043) { int tmp; CYCTOCK(4); RD_IMM; TMA; } OPEND(); // 4 TMA 83 OP(063) { ILL; } OPEND(); // 2 ??? 84 OP(083) { int tmp,tmp2; CYCTOCK(7); RD_IMM2; RD_ZPG; TST; WB_EAZ;} OPEND(); // 7 TST IMM,ZPG 85 OP(0a3) { int tmp,tmp2; CYCTOCK(7); RD_IMM2; RD_ZPX; TST; WB_EAZ;} OPEND(); // 7 TST IMM,ZPX 86 OP(0c3) { int to,from,length; TDD; } OPEND(); // 6*l+17 TDD XFER 87 OP(0e3) { int to,from,length,alternate; TIA; } OPEND(); // 6*l+17 TIA XFER 88 89 OP(013) { int tmp; CYCTOCK(4); RD_IMM; ST1; } OPEND(); // 4 ST1 90 OP(033) { ILL; } OPEND(); // 2 ??? 91 OP(053) { int tmp; CYCTOCK(5); RD_IMM; TAM; } OPEND(); // 5 TAM IMM 92 OP(073) { int to,from,length; TII; } OPEND(); // 6*l+17 TII XFER 93 OP(093) { int tmp,tmp2; CYCTOCK(8); RD_IMM2; RD_ABS; TST; WB_EA;} OPEND(); // 8 TST IMM,ABS 94 OP(0b3) { int tmp,tmp2; CYCTOCK(8); RD_IMM2; RD_ABX; TST; WB_EA;} OPEND(); // 8 TST IMM,ABX 95 OP(0d3) { int to,from,length; TIN; } OPEND(); // 6*l+17 TIN XFER 96 OP(0f3) { int to,from,length,alternate; TAI; } OPEND(); // 6*l+17 TAI XFER 97 98 OP(004) { int tmp; CYCTOCK(6); RD_ZPG; TSB; WB_EAZ; } OPEND(); // 6 TSB ZPG 99 OP(024) { int tmp; CYCTOCK(4); RD_ZPG; BIT; } OPEND(); // 4 BIT ZPG 100 OP(044) { int tmp; BSR; } OPEND(); // 8 BSR REL 101 OP(064) { int tmp; CYCTOCK(4); STZ; WR_ZPG; } OPEND(); // 4 STZ ZPG 102 OP(084) { int tmp; CYCTOCK(4); STY; WR_ZPG; } OPEND(); // 4 STY ZPG 103 OP(0a4) { int tmp; CYCTOCK(4); RD_ZPG; LDY; } OPEND(); // 4 LDY ZPG 104 OP(0c4) { int tmp; CYCTOCK(4); RD_ZPG; CPY; } OPEND(); // 4 CPY ZPG 105 OP(0e4) { int tmp; CYCTOCK(4); RD_ZPG; CPX; } OPEND(); // 4 CPX ZPG 106 107 OP(014) { int tmp; CYCTOCK(6); RD_ZPG; TRB; WB_EAZ; } OPEND(); // 6 TRB ZPG 108 OP(034) { int tmp; CYCTOCK(4); RD_ZPX; BIT; } OPEND(); // 4 BIT ZPX 109 OP(054) { CYCTOCK(2); CSL; } OPEND(); // 2 CSL 110 OP(074) { int tmp; CYCTOCK(4); STZ; WR_ZPX; } OPEND(); // 4 STZ ZPX 111 OP(094) { int tmp; CYCTOCK(4); STY; WR_ZPX; } OPEND(); // 4 STY ZPX 112 OP(0b4) { int tmp; CYCTOCK(4); RD_ZPX; LDY; } OPEND(); // 4 LDY ZPX 113 OP(0d4) { CYCTOCK(2); CSH; } OPEND(); // 2 CSH 114 OP(0f4) { CYCTOCK(2); SET; } OPEND(); // 2 SET 115 116 OP(005) { int tmp; CYCTOCK(4); RD_ZPG; ORA; } OPEND(); // 4 ORA ZPG 117 OP(025) { int tmp; CYCTOCK(4); RD_ZPG; AND; } OPEND(); // 4 AND ZPG 118 OP(045) { int tmp; CYCTOCK(4); RD_ZPG; EOR; } OPEND(); // 4 EOR ZPG 119 OP(065) { int tmp; CYCTOCK(4); RD_ZPG; ADC; } OPEND(); // 4 ADC ZPG 120 OP(085) { int tmp; CYCTOCK(4); STA; WR_ZPG; } OPEND(); // 4 STA ZPG 121 OP(0a5) { int tmp; CYCTOCK(4); RD_ZPG; LDA; } OPEND(); // 4 LDA ZPG 122 OP(0c5) { int tmp; CYCTOCK(4); RD_ZPG; CMP; } OPEND(); // 4 CMP ZPG 123 OP(0e5) { int tmp; CYCTOCK(4); RD_ZPG; SBC; } OPEND(); // 4 SBC ZPG 124 125 OP(015) { int tmp; CYCTOCK(4); RD_ZPX; ORA; } OPEND(); // 4 ORA ZPX 126 OP(035) { int tmp; CYCTOCK(4); RD_ZPX; AND; } OPEND(); // 4 AND ZPX 127 OP(055) { int tmp; CYCTOCK(4); RD_ZPX; EOR; } OPEND(); // 4 EOR ZPX 128 OP(075) { int tmp; CYCTOCK(4); RD_ZPX; ADC; } OPEND(); // 4 ADC ZPX 129 OP(095) { int tmp; CYCTOCK(4); STA; WR_ZPX; } OPEND(); // 4 STA ZPX 130 OP(0b5) { int tmp; CYCTOCK(4); RD_ZPX; LDA; } OPEND(); // 4 LDA ZPX 131 OP(0d5) { int tmp; CYCTOCK(4); RD_ZPX; CMP; } OPEND(); // 4 CMP ZPX 132 OP(0f5) { int tmp; CYCTOCK(4); RD_ZPX; SBC; } OPEND(); // 4 SBC ZPX 133 134 OP(006) { int tmp; CYCTOCK(6); RD_ZPG; ASL; WB_EAZ; } OPEND(); // 6 ASL ZPG 135 OP(026) { int tmp; CYCTOCK(6); RD_ZPG; ROL; WB_EAZ; } OPEND(); // 6 ROL ZPG 136 OP(046) { int tmp; CYCTOCK(6); RD_ZPG; LSR; WB_EAZ; } OPEND(); // 6 LSR ZPG 137 OP(066) { int tmp; CYCTOCK(6); RD_ZPG; ROR; WB_EAZ; } OPEND(); // 6 ROR ZPG 138 OP(086) { int tmp; CYCTOCK(4); STX; WR_ZPG; } OPEND(); // 4 STX ZPG 139 OP(0a6) { int tmp; CYCTOCK(4); RD_ZPG; LDX; } OPEND(); // 4 LDX ZPG 140 OP(0c6) { int tmp; CYCTOCK(6); RD_ZPG; DEC; WB_EAZ; } OPEND(); // 6 DEC ZPG 141 OP(0e6) { int tmp; CYCTOCK(6); RD_ZPG; INC; WB_EAZ; } OPEND(); // 6 INC ZPG 142 143 OP(016) { int tmp; CYCTOCK(6); RD_ZPX; ASL; WB_EAZ } OPEND(); // 6 ASL ZPX 144 OP(036) { int tmp; CYCTOCK(6); RD_ZPX; ROL; WB_EAZ } OPEND(); // 6 ROL ZPX 145 OP(056) { int tmp; CYCTOCK(6); RD_ZPX; LSR; WB_EAZ } OPEND(); // 6 LSR ZPX 146 OP(076) { int tmp; CYCTOCK(6); RD_ZPX; ROR; WB_EAZ } OPEND(); // 6 ROR ZPX 147 OP(096) { int tmp; CYCTOCK(4); STX; WR_ZPY; } OPEND(); // 4 STX ZPY 148 OP(0b6) { int tmp; CYCTOCK(4); RD_ZPY; LDX; } OPEND(); // 4 LDX ZPY 149 OP(0d6) { int tmp; CYCTOCK(6); RD_ZPX; DEC; WB_EAZ; } OPEND(); // 6 DEC ZPX 150 OP(0f6) { int tmp; CYCTOCK(6); RD_ZPX; INC; WB_EAZ; } OPEND(); // 6 INC ZPX 151 152 OP(007) { int tmp; CYCTOCK(7); RD_ZPG; RMB(0);WB_EAZ;} OPEND(); // 7 RMB0 ZPG 153 OP(027) { int tmp; CYCTOCK(7); RD_ZPG; RMB(2);WB_EAZ;} OPEND(); // 7 RMB2 ZPG 154 OP(047) { int tmp; CYCTOCK(7); RD_ZPG; RMB(4);WB_EAZ;} OPEND(); // 7 RMB4 ZPG 155 OP(067) { int tmp; CYCTOCK(7); RD_ZPG; RMB(6);WB_EAZ;} OPEND(); // 7 RMB6 ZPG 156 OP(087) { int tmp; CYCTOCK(7); RD_ZPG; SMB(0);WB_EAZ;} OPEND(); // 7 SMB0 ZPG 157 OP(0a7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(2);WB_EAZ;} OPEND(); // 7 SMB2 ZPG 158 OP(0c7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(4);WB_EAZ;} OPEND(); // 7 SMB4 ZPG 159 OP(0e7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(6);WB_EAZ;} OPEND(); // 7 SMB6 ZPG 160 161 OP(017) { int tmp; CYCTOCK(7); RD_ZPG; RMB(1);WB_EAZ;} OPEND(); // 7 RMB1 ZPG 162 OP(037) { int tmp; CYCTOCK(7); RD_ZPG; RMB(3);WB_EAZ;} OPEND(); // 7 RMB3 ZPG 163 OP(057) { int tmp; CYCTOCK(7); RD_ZPG; RMB(5);WB_EAZ;} OPEND(); // 7 RMB5 ZPG 164 OP(077) { int tmp; CYCTOCK(7); RD_ZPG; RMB(7);WB_EAZ;} OPEND(); // 7 RMB7 ZPG 165 OP(097) { int tmp; CYCTOCK(7); RD_ZPG; SMB(1);WB_EAZ;} OPEND(); // 7 SMB1 ZPG 166 OP(0b7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(3);WB_EAZ;} OPEND(); // 7 SMB3 ZPG 167 OP(0d7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(5);WB_EAZ;} OPEND(); // 7 SMB5 ZPG 168 OP(0f7) { int tmp; CYCTOCK(7); RD_ZPG; SMB(7);WB_EAZ;} OPEND(); // 7 SMB7 ZPG 169 170 OP(008) { CYCTOCK(3); PHP; } OPEND(); // 3 PHP 171 OP(028) { CYCTOCK(4); PLP; } OPEND(); // 4 PLP 172 OP(048) { CYCTOCK(3); PHA; } OPEND(); // 3 PHA 173 OP(068) { CYCTOCK(4); PLA; } OPEND(); // 4 PLA 174 OP(088) { CYCTOCK(2); DEY; } OPEND(); // 2 DEY 175 OP(0a8) { CYCTOCK(2); TAY; } OPEND(); // 2 TAY 176 OP(0c8) { CYCTOCK(2); INY; } OPEND(); // 2 INY 177 OP(0e8) { CYCTOCK(2); INX; } OPEND(); // 2 INX 178 179 OP(018) { CYCTOCK(2); CLC; } OPEND(); // 2 CLC 180 OP(038) { CYCTOCK(2); SEC; } OPEND(); // 2 SEC 181 OP(058) { CYCTOCK(2); CLI; } OPEND(); // 2 CLI 182 OP(078) { CYCTOCK(2); SEI; } OPEND(); // 2 SEI 183 OP(098) { CYCTOCK(2); TYA; } OPEND(); // 2 TYA 184 OP(0b8) { CYCTOCK(2); CLV; } OPEND(); // 2 CLV 185 OP(0d8) { CYCTOCK(2); CLD; } OPEND(); // 2 CLD 186 OP(0f8) { CYCTOCK(2); SED; } OPEND(); // 2 SED 187 188 OP(009) { int tmp; CYCTOCK(2); RD_IMM; ORA; } OPEND(); // 2 ORA IMM 189 OP(029) { int tmp; CYCTOCK(2); RD_IMM; AND; } OPEND(); // 2 AND IMM 190 OP(049) { int tmp; CYCTOCK(2); RD_IMM; EOR; } OPEND(); // 2 EOR IMM 191 OP(069) { int tmp; CYCTOCK(2); RD_IMM; ADC; } OPEND(); // 2 ADC IMM 192 OP(089) { int tmp; CYCTOCK(2); RD_IMM; BIT; } OPEND(); // 2 BIT IMM 193 OP(0a9) { int tmp; CYCTOCK(2); RD_IMM; LDA; } OPEND(); // 2 LDA IMM 194 OP(0c9) { int tmp; CYCTOCK(2); RD_IMM; CMP; } OPEND(); // 2 CMP IMM 195 OP(0e9) { int tmp; CYCTOCK(2); RD_IMM; SBC; } OPEND(); // 2 SBC IMM 196 197 OP(019) { int tmp; CYCTOCK(5); RD_ABY; ORA; } OPEND(); // 5 ORA ABY 198 OP(039) { int tmp; CYCTOCK(5); RD_ABY; AND; } OPEND(); // 5 AND ABY 199 OP(059) { int tmp; CYCTOCK(5); RD_ABY; EOR; } OPEND(); // 5 EOR ABY 200 OP(079) { int tmp; CYCTOCK(5); RD_ABY; ADC; } OPEND(); // 5 ADC ABY 201 OP(099) { int tmp; CYCTOCK(5); STA; WR_ABY; } OPEND(); // 5 STA ABY 202 OP(0b9) { int tmp; CYCTOCK(5); RD_ABY; LDA; } OPEND(); // 5 LDA ABY 203 OP(0d9) { int tmp; CYCTOCK(5); RD_ABY; CMP; } OPEND(); // 5 CMP ABY 204 OP(0f9) { int tmp; CYCTOCK(5); RD_ABY; SBC; } OPEND(); // 5 SBC ABY 205 206 OP(00a) { int tmp; CYCTOCK(2); RD_ACC; ASL; WB_ACC; } OPEND(); // 2 ASL A 207 OP(02a) { int tmp; CYCTOCK(2); RD_ACC; ROL; WB_ACC; } OPEND(); // 2 ROL A 208 OP(04a) { int tmp; CYCTOCK(2); RD_ACC; LSR; WB_ACC; } OPEND(); // 2 LSR A 209 OP(06a) { int tmp; CYCTOCK(2); RD_ACC; ROR; WB_ACC; } OPEND(); // 2 ROR A 210 OP(08a) { CYCTOCK(2); TXA; } OPEND(); // 2 TXA 211 OP(0aa) { CYCTOCK(2); TAX; } OPEND(); // 2 TAX 212 OP(0ca) { CYCTOCK(2); DEX; } OPEND(); // 2 DEX 213 OP(0ea) { CYCTOCK(2); NOP; } OPEND(); // 2 NOP 214 215 OP(01a) { CYCTOCK(2); INA; } OPEND(); // 2 INC A 216 OP(03a) { CYCTOCK(2); DEA; } OPEND(); // 2 DEC A 217 OP(05a) { CYCTOCK(3); PHY; } OPEND(); // 3 PHY 218 OP(07a) { CYCTOCK(4); PLY; } OPEND(); // 4 PLY 219 OP(09a) { CYCTOCK(2); TXS; } OPEND(); // 2 TXS 220 OP(0ba) { CYCTOCK(2); TSX; } OPEND(); // 2 TSX 221 OP(0da) { CYCTOCK(3); PHX; } OPEND(); // 3 PHX 222 OP(0fa) { CYCTOCK(4); PLX; } OPEND(); // 4 PLX 223 224 OP(00b) { ILL; } OPEND(); // 2 ??? 225 OP(02b) { ILL; } OPEND(); // 2 ??? 226 OP(04b) { ILL; } OPEND(); // 2 ??? 227 OP(06b) { ILL; } OPEND(); // 2 ??? 228 OP(08b) { ILL; } OPEND(); // 2 ??? 229 OP(0ab) { ILL; } OPEND(); // 2 ??? 230 OP(0cb) { ILL; } OPEND(); // 2 ??? 231 OP(0eb) { ILL; } OPEND(); // 2 ??? 232 233 OP(01b) { ILL; } OPEND(); // 2 ??? 234 OP(03b) { ILL; } OPEND(); // 2 ??? 235 OP(05b) { ILL; } OPEND(); // 2 ??? 236 OP(07b) { ILL; } OPEND(); // 2 ??? 237 OP(09b) { ILL; } OPEND(); // 2 ??? 238 OP(0bb) { ILL; } OPEND(); // 2 ??? 239 OP(0db) { ILL; } OPEND(); // 2 ??? 240 OP(0fb) { ILL; } OPEND(); // 2 ??? 241 242 OP(00c) { int tmp; CYCTOCK(7); RD_ABS; TSB; WB_EA; } OPEND(); // 7 TSB ABS 243 OP(02c) { int tmp; CYCTOCK(5); RD_ABS; BIT; } OPEND(); // 5 BIT ABS 244 OP(04c) { CYCTOCK(4); EA_ABS; JMP; } OPEND(); // 4 JMP ABS 245 OP(06c) { int tmp; CYCTOCK(7); EA_IND; JMP; } OPEND(); // 7 JMP IND 246 OP(08c) { int tmp; CYCTOCK(5); STY; WR_ABS; } OPEND(); // 5 STY ABS 247 OP(0ac) { int tmp; CYCTOCK(5); RD_ABS; LDY; } OPEND(); // 5 LDY ABS 248 OP(0cc) { int tmp; CYCTOCK(5); RD_ABS; CPY; } OPEND(); // 5 CPY ABS 249 OP(0ec) { int tmp; CYCTOCK(5); RD_ABS; CPX; } OPEND(); // 5 CPX ABS 250 251 OP(01c) { int tmp; CYCTOCK(7); RD_ABS; TRB; WB_EA; } OPEND(); // 7 TRB ABS 252 OP(03c) { int tmp; CYCTOCK(5); RD_ABX; BIT; } OPEND(); // 5 BIT ABX 253 OP(05c) { ILL; } OPEND(); // 2 ??? 254 OP(07c) { int tmp; CYCTOCK(7); EA_IAX; JMP; } OPEND(); // 7 JMP IAX 255 OP(09c) { int tmp; CYCTOCK(5); STZ; WR_ABS; } OPEND(); // 5 STZ ABS 256 OP(0bc) { int tmp; CYCTOCK(5); RD_ABX; LDY; } OPEND(); // 5 LDY ABX 257 OP(0dc) { ILL; } OPEND(); // 2 ??? 258 259 OP(0fc) { ILL; } OPEND(); // 2 ??? 260 261 OP(00d) { int tmp; CYCTOCK(5); RD_ABS; ORA; } OPEND(); // 5 ORA ABS 262 OP(02d) { int tmp; CYCTOCK(5); RD_ABS; AND; } OPEND(); // 4 AND ABS 263 OP(04d) { int tmp; CYCTOCK(5); RD_ABS; EOR; } OPEND(); // 4 EOR ABS 264 OP(06d) { int tmp; CYCTOCK(5); RD_ABS; ADC; } OPEND(); // 4 ADC ABS 265 OP(08d) { int tmp; CYCTOCK(5); STA; WR_ABS; } OPEND(); // 4 STA ABS 266 OP(0ad) { int tmp; CYCTOCK(5); RD_ABS; LDA; } OPEND(); // 4 LDA ABS 267 OP(0cd) { int tmp; CYCTOCK(5); RD_ABS; CMP; } OPEND(); // 4 CMP ABS 268 OP(0ed) { int tmp; CYCTOCK(5); RD_ABS; SBC; } OPEND(); // 4 SBC ABS 269 270 OP(01d) { int tmp; CYCTOCK(5); RD_ABX; ORA; } OPEND(); // 5 ORA ABX 271 OP(03d) { int tmp; CYCTOCK(5); RD_ABX; AND; } OPEND(); // 4 AND ABX 272 OP(05d) { int tmp; CYCTOCK(5); RD_ABX; EOR; } OPEND(); // 4 EOR ABX 273 OP(07d) { int tmp; CYCTOCK(5); RD_ABX; ADC; } OPEND(); // 4 ADC ABX 274 OP(09d) { int tmp; CYCTOCK(5); STA; WR_ABX; } OPEND(); // 5 STA ABX 275 OP(0bd) { int tmp; CYCTOCK(5); RD_ABX; LDA; } OPEND(); // 5 LDA ABX 276 OP(0dd) { int tmp; CYCTOCK(5); RD_ABX; CMP; } OPEND(); // 4 CMP ABX 277 OP(0fd) { int tmp; CYCTOCK(5); RD_ABX; SBC; } OPEND(); // 4 SBC ABX 278 279 OP(00e) { int tmp; CYCTOCK(7); RD_ABS; ASL; WB_EA; } OPEND(); // 6 ASL ABS 280 OP(02e) { int tmp; CYCTOCK(7); RD_ABS; ROL; WB_EA; } OPEND(); // 6 ROL ABS 281 OP(04e) { int tmp; CYCTOCK(7); RD_ABS; LSR; WB_EA; } OPEND(); // 6 LSR ABS 282 OP(06e) { int tmp; CYCTOCK(7); RD_ABS; ROR; WB_EA; } OPEND(); // 6 ROR ABS 283 OP(08e) { int tmp; CYCTOCK(5); STX; WR_ABS; } OPEND(); // 4 STX ABS 284 OP(0ae) { int tmp; CYCTOCK(5); RD_ABS; LDX; } OPEND(); // 5 LDX ABS 285 OP(0ce) { int tmp; CYCTOCK(7); RD_ABS; DEC; WB_EA; } OPEND(); // 6 DEC ABS 286 OP(0ee) { int tmp; CYCTOCK(7); RD_ABS; INC; WB_EA; } OPEND(); // 6 INC ABS 287 288 OP(01e) { int tmp; CYCTOCK(7); RD_ABX; ASL; WB_EA; } OPEND(); // 7 ASL ABX 289 OP(03e) { int tmp; CYCTOCK(7); RD_ABX; ROL; WB_EA; } OPEND(); // 7 ROL ABX 290 OP(05e) { int tmp; CYCTOCK(7); RD_ABX; LSR; WB_EA; } OPEND(); // 7 LSR ABX 291 OP(07e) { int tmp; CYCTOCK(7); RD_ABX; ROR; WB_EA; } OPEND(); // 7 ROR ABX 292 OP(09e) { int tmp; CYCTOCK(5); STZ; WR_ABX; } OPEND(); // 5 STZ ABX 293 OP(0be) { int tmp; CYCTOCK(5); RD_ABY; LDX; } OPEND(); // 4 LDX ABY 294 OP(0de) { int tmp; CYCTOCK(7); RD_ABX; DEC; WB_EA; } OPEND(); // 7 DEC ABX 295 OP(0fe) { int tmp; CYCTOCK(7); RD_ABX; INC; WB_EA; } OPEND(); // 7 INC ABX 296 297 OP(00f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(0); } OPEND(); // 6/8 BBR0 ZPG,REL 298 OP(02f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(2); } OPEND(); // 6/8 BBR2 ZPG,REL 299 OP(04f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(4); } OPEND(); // 6/8 BBR4 ZPG,REL 300 OP(06f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(6); } OPEND(); // 6/8 BBR6 ZPG,REL 301 OP(08f) { int tmp; CYCTOCK(4); RD_ZPG; BBS(0); } OPEND(); // 6/8 BBS0 ZPG,REL 302 OP(0af) { int tmp; CYCTOCK(4); RD_ZPG; BBS(2); } OPEND(); // 6/8 BBS2 ZPG,REL 303 OP(0cf) { int tmp; CYCTOCK(4); RD_ZPG; BBS(4); } OPEND(); // 6/8 BBS4 ZPG,REL 304 OP(0ef) { int tmp; CYCTOCK(4); RD_ZPG; BBS(6); } OPEND(); // 6/8 BBS6 ZPG,REL 305 306 OP(01f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(1); } OPEND(); // 6/8 BBR1 ZPG,REL 307 OP(03f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(3); } OPEND(); // 6/8 BBR3 ZPG,REL 308 OP(05f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(5); } OPEND(); // 6/8 BBR5 ZPG,REL 309 OP(07f) { int tmp; CYCTOCK(4); RD_ZPG; BBR(7); } OPEND(); // 6/8 BBR7 ZPG,REL 310 OP(09f) { int tmp; CYCTOCK(4); RD_ZPG; BBS(1); } OPEND(); // 6/8 BBS1 ZPG,REL 311 OP(0bf) { int tmp; CYCTOCK(4); RD_ZPG; BBS(3); } OPEND(); // 6/8 BBS3 ZPG,REL 312 OP(0df) { int tmp; CYCTOCK(4); RD_ZPG; BBS(5); } OPEND(); // 6/8 BBS5 ZPG,REL 313 OP(0ff) { int tmp; CYCTOCK(4); RD_ZPG; BBS(7); } OPEND(); // 6/8 BBS7 ZPG,REL 314 315 /* 316 static void (*insnh6280[0x100])(h6280_Regs *) = { 317 h6280_000,h6280_001,h6280_002,h6280_003,h6280_004,h6280_005,h6280_006,h6280_007, 318 h6280_008,h6280_009,h6280_00a,h6280_00b,h6280_00c,h6280_00d,h6280_00e,h6280_00f, 319 h6280_010,h6280_011,h6280_012,h6280_013,h6280_014,h6280_015,h6280_016,h6280_017, 320 h6280_018,h6280_019,h6280_01a,h6280_01b,h6280_01c,h6280_01d,h6280_01e,h6280_01f, 321 h6280_020,h6280_021,h6280_022,h6280_023,h6280_024,h6280_025,h6280_026,h6280_027, 322 h6280_028,h6280_029,h6280_02a,h6280_02b,h6280_02c,h6280_02d,h6280_02e,h6280_02f, 323 h6280_030,h6280_031,h6280_032,h6280_033,h6280_034,h6280_035,h6280_036,h6280_037, 324 h6280_038,h6280_039,h6280_03a,h6280_03b,h6280_03c,h6280_03d,h6280_03e,h6280_03f, 325 h6280_040,h6280_041,h6280_042,h6280_043,h6280_044,h6280_045,h6280_046,h6280_047, 326 h6280_048,h6280_049,h6280_04a,h6280_04b,h6280_04c,h6280_04d,h6280_04e,h6280_04f, 327 h6280_050,h6280_051,h6280_052,h6280_053,h6280_054,h6280_055,h6280_056,h6280_057, 328 h6280_058,h6280_059,h6280_05a,h6280_05b,h6280_05c,h6280_05d,h6280_05e,h6280_05f, 329 h6280_060,h6280_061,h6280_062,h6280_063,h6280_064,h6280_065,h6280_066,h6280_067, 330 h6280_068,h6280_069,h6280_06a,h6280_06b,h6280_06c,h6280_06d,h6280_06e,h6280_06f, 331 h6280_070,h6280_071,h6280_072,h6280_073,h6280_074,h6280_075,h6280_076,h6280_077, 332 h6280_078,h6280_079,h6280_07a,h6280_07b,h6280_07c,h6280_07d,h6280_07e,h6280_07f, 333 h6280_080,h6280_081,h6280_082,h6280_083,h6280_084,h6280_085,h6280_086,h6280_087, 334 h6280_088,h6280_089,h6280_08a,h6280_08b,h6280_08c,h6280_08d,h6280_08e,h6280_08f, 335 h6280_090,h6280_091,h6280_092,h6280_093,h6280_094,h6280_095,h6280_096,h6280_097, 336 h6280_098,h6280_099,h6280_09a,h6280_09b,h6280_09c,h6280_09d,h6280_09e,h6280_09f, 337 h6280_0a0,h6280_0a1,h6280_0a2,h6280_0a3,h6280_0a4,h6280_0a5,h6280_0a6,h6280_0a7, 338 h6280_0a8,h6280_0a9,h6280_0aa,h6280_0ab,h6280_0ac,h6280_0ad,h6280_0ae,h6280_0af, 339 h6280_0b0,h6280_0b1,h6280_0b2,h6280_0b3,h6280_0b4,h6280_0b5,h6280_0b6,h6280_0b7, 340 h6280_0b8,h6280_0b9,h6280_0ba,h6280_0bb,h6280_0bc,h6280_0bd,h6280_0be,h6280_0bf, 341 h6280_0c0,h6280_0c1,h6280_0c2,h6280_0c3,h6280_0c4,h6280_0c5,h6280_0c6,h6280_0c7, 342 h6280_0c8,h6280_0c9,h6280_0ca,h6280_0cb,h6280_0cc,h6280_0cd,h6280_0ce,h6280_0cf, 343 h6280_0d0,h6280_0d1,h6280_0d2,h6280_0d3,h6280_0d4,h6280_0d5,h6280_0d6,h6280_0d7, 344 h6280_0d8,h6280_0d9,h6280_0da,h6280_0db,h6280_0dc,h6280_0dd,h6280_0de,h6280_0df, 345 h6280_0e0,h6280_0e1,h6280_0e2,h6280_0e3,h6280_0e4,h6280_0e5,h6280_0e6,h6280_0e7, 346 h6280_0e8,h6280_0e9,h6280_0ea,h6280_0eb,h6280_0ec,h6280_0ed,h6280_0ee,h6280_0ef, 347 h6280_0f0,h6280_0f1,h6280_0f2,h6280_0f3,h6280_0f4,h6280_0f5,h6280_0f6,h6280_0f7, 348 h6280_0f8,h6280_0f9,h6280_0fa,h6280_0fb,h6280_0fc,h6280_0fd,h6280_0fe,h6280_0ff 349 }; 350 */ 351