src/include/cpu_sh.h

96 struct sh_cpu {  struct
97 	struct sh_cpu_type_def cpu_type;  argument
100 	uint32_t	r[SH_N_GPRS];
101 	uint32_t	r_bank[SH_N_GPRS_BANKED];
104 	uint32_t	fr[SH_N_FPRS];
105 	uint32_t	xf[SH_N_FPRS];	/*  "Other bank."  */
107 	uint32_t	mach;		/*  Multiply-Accumulate High  */
108 	uint32_t	macl;		/*  Multiply-Accumulate Low  */
109 	uint32_t	pr;		/*  Procedure Register  */
110 	uint32_t	fpscr;		/*  Floating-point Status/Control  */
111 	uint32_t	fpul;		/*  Floating-point Communication Reg  */
112 	uint32_t	sr;		/*  Status Register  */
113 	uint32_t	ssr;		/*  Saved Status Register  */
114 	uint32_t	spc;		/*  Saved PC  */
115 	uint32_t	gbr;		/*  Global Base Register  */
116 	uint32_t	vbr;		/*  Vector Base Register  */
117 	uint32_t	sgr;		/*  Saved General Register  */
118 	uint32_t	dbr;		/*  Debug Base Register  */
121 	uint32_t	ccr;		/*  Cache Control Register  */
122 	uint32_t	qacr0;		/*  Queue Address Control Register 0  */
123 	uint32_t	qacr1;		/*  Queue Address Control Register 1  */
126 	uint32_t	pteh;		/*  Page Table Entry High  */
127 	uint32_t	ptel;		/*  Page Table Entry Low  */
128 	uint32_t	ptea;		/*  Page Table Entry A  */
129 	uint32_t	ttb;		/*  Translation Table Base  */
130 	uint32_t	tea;		/*  TLB Exception Address Register  */
131 	uint32_t	mmucr;		/*  MMU Control Register  */
132 	uint32_t	itlb_hi[SH_N_ITLB_ENTRIES];
133 	uint32_t	itlb_lo[SH_N_ITLB_ENTRIES];
134 	uint32_t	utlb_hi[SH_N_UTLB_ENTRIES];
135 	uint32_t	utlb_lo[SH_N_UTLB_ENTRIES];
138 	uint32_t	tra;		/*  TRAPA Exception Register  */
139 	uint32_t	expevt;		/*  Exception Event Register  */
140 	uint32_t	intevt;		/*  Interrupt Event Register  */
143 	uint16_t	intc_ipra;	/*  Interrupt Priority Registers  */
144 	uint16_t	intc_iprb;
145 	uint16_t	intc_iprc;
146 	uint16_t	intc_iprd;
147 	uint32_t	intc_intpri00;
148 	uint32_t	intc_intpri04;
149 	uint32_t	intc_intpri08;
150 	uint32_t	intc_intpri0c;
151 	uint32_t	intc_intreq00;
152 	uint32_t	intc_intreq04;
153 	uint32_t	intc_intmsk00;
154 	uint32_t	intc_intmsk04;
156 	uint8_t		int_prio_and_pending[0x1000 / 0x20];
157 	int16_t		int_to_assert;	/*  Calculated int to assert  */
158 	unsigned int	int_level;	/*  Calculated int level  */
161 	int		pclock;
164 	uint32_t	dmac_sar[N_SH4_DMA_CHANNELS];
165 	uint32_t	dmac_dar[N_SH4_DMA_CHANNELS];
166 	uint32_t	dmac_tcr[N_SH4_DMA_CHANNELS];
167 	uint32_t	dmac_chcr[N_SH4_DMA_CHANNELS];
168 	uint32_t	dmaor;		/*  DMA operation register  */
171 	struct pci_data	*pcic_pcibus;