| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
|
| H A D | vuzp_half.c | 164 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
167 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vuzp_half() local
168 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vuzp_half() local
169 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
172 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vuzp_half() local
173 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vuzp_half() local
174 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
179 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0xca80, in exec_vuzp_half() local
182 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
190 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vuzp_half() local
[all …]
|
| H A D | vzip_half.c | 167 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf4, 0x11, 0xf5, 0x11, in exec_vzip_half() local
170 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vzip_half() local
171 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vzip_half() local
175 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vzip_half() local
176 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vzip_half() local
182 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb00, 0x4b4d, in exec_vzip_half() local
191 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff2, 0x33, in exec_vzip_half() local
193 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vzip_half() local
201 VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff2, 0x77, in exec_vzip_half() local
203 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1, in exec_vzip_half() local
[all …]
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| H A D | vtrn_half.c | 167 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0x11, 0xf3, 0x11, in exec_vtrn_half() local
170 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vtrn_half() local
171 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vtrn_half() local
175 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vtrn_half() local
176 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vtrn_half() local
182 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0x4b4d, in exec_vtrn_half() local
191 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0x33, in exec_vtrn_half() local
193 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vtrn_half() local
201 VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0x77, in exec_vtrn_half() local
203 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1, in exec_vtrn_half() local
[all …]
|
| /dports/lang/gcc10/gcc-10.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| H A D | vtrn_half.c | 164 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0x11, 0xf3, 0x11, in exec_vtrn_half() local
167 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vtrn_half() local
168 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vtrn_half() local
172 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vtrn_half() local
173 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vtrn_half() local
179 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0x4b4d, in exec_vtrn_half() local
188 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0x33, in exec_vtrn_half() local
190 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vtrn_half() local
198 VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0x77, in exec_vtrn_half() local
200 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1, in exec_vtrn_half() local
[all …]
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| H A D | vuzp_half.c | 161 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
164 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vuzp_half() local
165 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vuzp_half() local
166 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
169 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vuzp_half() local
170 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vuzp_half() local
171 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
176 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0xca80, in exec_vuzp_half() local
179 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
187 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vuzp_half() local
[all …]
|
| H A D | vzip_half.c | 164 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf4, 0x11, 0xf5, 0x11, in exec_vzip_half() local
167 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vzip_half() local
168 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vzip_half() local
172 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vzip_half() local
173 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vzip_half() local
179 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb00, 0x4b4d, in exec_vzip_half() local
188 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff2, 0x33, in exec_vzip_half() local
190 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vzip_half() local
198 VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff2, 0x77, in exec_vzip_half() local
200 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1, in exec_vzip_half() local
[all …]
|
| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
|
| H A D | vzip_half.c | 167 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf4, 0x11, 0xf5, 0x11, in exec_vzip_half() local
170 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vzip_half() local
171 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vzip_half() local
175 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vzip_half() local
176 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vzip_half() local
182 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb00, 0x4b4d, in exec_vzip_half() local
191 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff2, 0x33, in exec_vzip_half() local
193 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vzip_half() local
201 VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff2, 0x77, in exec_vzip_half() local
203 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1, in exec_vzip_half() local
[all …]
|
| H A D | vtrn_half.c | 167 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0x11, 0xf3, 0x11, in exec_vtrn_half() local
170 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vtrn_half() local
171 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vtrn_half() local
175 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vtrn_half() local
176 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vtrn_half() local
182 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0x4b4d, in exec_vtrn_half() local
191 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0x33, in exec_vtrn_half() local
193 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vtrn_half() local
201 VECT_VAR_DECL(expected2,uint,32,4) [] = { 0xfffffff1, 0x77, in exec_vtrn_half() local
203 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff1, in exec_vtrn_half() local
[all …]
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| H A D | vuzp_half.c | 164 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
167 VECT_VAR_DECL(expected2,int,32,2) [] = { 0xfffffff1, 0x33 }; in exec_vuzp_half() local
168 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff1 }; in exec_vuzp_half() local
169 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
172 VECT_VAR_DECL(expected2,uint,32,2) [] = { 0xfffffff1, 0x77 }; in exec_vuzp_half() local
173 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff1 }; in exec_vuzp_half() local
174 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
179 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xcb80, 0xca80, in exec_vuzp_half() local
182 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xf1, 0xf3, 0xf5, 0xf7, in exec_vuzp_half() local
190 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff1, in exec_vuzp_half() local
[all …]
|
| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
|
| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
|
| /dports/lang/gcc8/gcc-8.5.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/devel/avr-gcc/gcc-10.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/lang/gcc11/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/lang/gcc9/gcc-9.4.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/lang/gcc10-devel/gcc-10-20211008/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ |
| H A D | vdup_lane.c | 124 VECT_VAR_DECL(expected2,int,8,8) [] = { 0xfd, 0xfd, 0xfd, 0xfd, in exec_vdup_lane() local
128 VECT_VAR_DECL(expected2,int,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
129 VECT_VAR_DECL(expected2,uint,8,8) [] = { 0xff, 0xff, 0xff, 0xff, in exec_vdup_lane() local
133 VECT_VAR_DECL(expected2,uint,64,1) [] = { 0xfffffffffffffff0 }; in exec_vdup_lane() local
134 VECT_VAR_DECL(expected2,poly,8,8) [] = { 0xf7, 0xf7, 0xf7, 0xf7, in exec_vdup_lane() local
139 VECT_VAR_DECL (expected2, hfloat, 16, 4) [] = { 0xca80, 0xca80, in exec_vdup_lane() local
142 VECT_VAR_DECL(expected2,int,8,16) [] = { 0xfb, 0xfb, 0xfb, 0xfb, in exec_vdup_lane() local
148 VECT_VAR_DECL(expected2,int,32,4) [] = { 0xfffffff1, 0xfffffff1, in exec_vdup_lane() local
150 VECT_VAR_DECL(expected2,int,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
160 VECT_VAR_DECL(expected2,uint,64,2) [] = { 0xfffffffffffffff0, in exec_vdup_lane() local
[all …]
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