/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsCCState.h | 101 : CCState(CC, isVarArg, MF, locs, C), SpecialCallingConv(SpecialCC) {} in CCState() argument
|
H A D | MipsFastISel.cpp | 1133 CallingConv::ID CC = CLI.CallConv; in processCallArgs() local 1272 CallingConv::ID CC = CLI.CallConv; in finishCall() local 1319 CallingConv::ID CC = F->getCallingConv(); in fastLowerArguments() local 1487 CallingConv::ID CC = CLI.CallConv; in fastLowerCall() local 1685 CallingConv::ID CC = F.getCallingConv(); in selectRet() local
|
H A D | MipsISelLowering.cpp | 100 CallingConv::ID CC, in getRegisterTypeForCallingConv() 112 CallingConv::ID CC, in getNumRegistersForCallingConv() 124 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() 597 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { in condCodeToFCC() 625 static bool invertFPCondCodeUser(Mips::CondCode CC) { in invertFPCondCodeUser() 652 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in createFPCmp() local 661 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); in createCMovFP() local 702 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine() local 739 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in performSELECTCombine() local 2045 Mips::CondCode CC = (Mips::CondCode)CCNode->getAsZExtVal(); in lowerBRCOND() local
|
H A D | MipsSEISelLowering.cpp | 942 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) { in isLegalDSPCondCode()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 555 unsigned PTXCmpMode = [](ISD::CondCode CC) { in getPTXCmpMode()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCCCState.h | 33 PPCCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, in PPCCCState() 46 AIXCCState(CallingConv::ID CC, bool IsVarArg, MachineFunction &MF, in AIXCCState()
|
H A D | PPCFastISel.cpp | 1378 CallingConv::ID CC, in processCallArgs() 1490 CallingConv::ID CC = CLI.CallConv; in finishCall() local 1549 CallingConv::ID CC = CLI.CallConv; in fastLowerCall() local 1702 CallingConv::ID CC = F.getCallingConv(); in SelectRet() local
|
H A D | PPCISelDAGToDAG.cpp | 3330 ISD::CondCode CC, in get32BitZExtCompare() 3503 ISD::CondCode CC, in get32BitSExtCompare() 3675 ISD::CondCode CC, in get64BitZExtCompare() 3832 ISD::CondCode CC, in get64BitSExtCompare() 4032 ISD::CondCode CC = in getSETCCInGPR() local 4337 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) { in getCRIdxForSetCC() 4370 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC, in getVCmpInst() 4488 ISD::CondCode CC = in trySETCC() local 4858 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); in tryFoldSWTestBRCC() local 4908 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); in trySelectLoopCountIntrinsic() local [all …]
|
H A D | PPCISelLowering.cpp | 3614 ISD::CondCode CC = in LowerSETCC() local 3742 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, in LowerVAARG() local 4922 auto isTailCallableCC = [] (CallingConv::ID CC){ in areCallingConvEligibleForTCO_64SVR4() 8038 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC() local 10899 ISD::CondCode CC = ISD::SETGT; in LowerINTRINSIC_WO_CHAIN() local 13835 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); in ConvertSETCCToSubtract() local 13884 ISD::CondCode CC = in DAGCombineTruncBoolExt() local 14414 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); in combineSetCC() local 16237 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); in PerformDAGCombine() local 18537 CCAssignFn *PPCTargetLowering::ccAssignFnForCall(CallingConv::ID CC, in ccAssignFnForCall()
|
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
H A D | RISCVCallLowering.cpp | 397 CallingConv::ID CC = F.getCallingConv(); in lowerReturnVal() local 513 CallingConv::ID CC = F.getCallingConv(); in lowerFormalArguments() local 552 CallingConv::ID CC = F.getCallingConv(); in lowerCall() local
|
H A D | RISCVInstructionSelector.cpp | 413 static RISCVCC::CondCode getRISCVCCFromICmp(CmpInst::Predicate CC) { in getRISCVCCFromICmp() 433 RISCVCC::CondCode &CC, Register &LHS, in getOperandsForBranch() 611 RISCVCC::CondCode CC; in select() local 1098 RISCVCC::CondCode CC; in selectSelect() local
|
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVExpandPseudoInsts.cpp | 186 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm()); in expandCCOp() local
|
H A D | RISCVISelDAGToDAG.h | 166 static RISCVCC::CondCode getRISCVCCForIntCC(ISD::CondCode CC) { in getRISCVCCForIntCC()
|
H A D | RISCVISelLowering.cpp | 1901 SDValue X, ConstantSDNode *XC, ConstantSDNode *CC, SDValue Y, in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd() 6485 SDValue CC = Op.getOperand(4); in LowerOperation() local 7035 ISD::CondCode CC, SDValue Val) { in matchSetCC() 7456 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); in lowerShiftLeftParts() local 7508 SDValue CC = DAG.getSetCC(DL, VT, ShamtMinusXLen, Zero, ISD::SETLT); in lowerShiftRightParts() local 9120 ISD::CondCode CC; in lowerVectorMaskVecReduction() local 10237 SDValue CC = Op.getOperand(3); in lowerVectorStrictFSetcc() local 10385 SDValue CC = in lowerFixedLengthVectorSelectToRVV() local 12806 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); in performXORCombine() local 15397 SDValue CC = N->getOperand(2); in PerformDAGCombine() local [all …]
|
H A D | RISCVInstrInfo.cpp | 903 unsigned CC = getCondFromBranchOpc(LastInst.getOpcode()); in parseCondBranch() local 909 unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC) { in getBrCond() 932 RISCVCC::CondCode RISCVCC::getOppositeBranchCondition(RISCVCC::CondCode CC) { in getOppositeBranchCondition() 1077 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); in insertBranch() local 1162 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); in reverseBranchCondition() local 1177 RISCVCC::CondCode CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); in optimizeCondBranch() local 1461 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm()); in optimizeSelect() local 2821 auto CC = static_cast<RISCVCC::CondCode>(MI.getOperand(3).getImm()); in commuteInstructionImpl() local
|
H A D | RISCVRedundantCopyElimination.cpp | 79 auto CC = static_cast<RISCVCC::CondCode>(Cond[0].getImm()); in guaranteesZeroRegInBlock() local
|
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
H A D | SPIRVISelLowering.cpp | 22 LLVMContext &Context, CallingConv::ID CC, EVT VT) const { in getNumRegistersForCallingConv() 36 CallingConv::ID CC, in getRegisterTypeForCallingConv()
|
H A D | SPIRVPreLegalizer.cpp | 536 const auto CC = static_cast<CmpInst::Predicate>(PredOp.getPredicate()); in processSwitches() local
|
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcInstPrinter.cpp | 177 int CC = (int)MI->getOperand(opNum).getImm(); in printCCOperand() local
|
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | Sparc.h | 105 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { in SPARCCondCodeToString()
|
H A D | SparcISelLowering.cpp | 1519 static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) { in intCondCCodeToRcond() 1540 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { in IntCondCCodeToICC() 1558 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { in FPCondCCodeToFCC() 2086 ISD::CondCode CC, unsigned &SPCC) { in LookThroughSetCC() 2633 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC() local 2685 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC() local 3372 unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm(); in expandSelectCC() local
|
H A D | SparcInstrInfo.cpp | 84 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) in GetOppositeBranchCondition() 195 int64_t CC = LastInst->getOperand(1).getImm(); in parseCondBranch() local 347 unsigned CC = Cond[1].getImm(); in insertBranch() local 396 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[1].getImm()); in reverseBranchCondition() local
|
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZCallingConv.h | 47 SystemZCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, in SystemZCCState()
|
H A D | SystemZISelLowering.cpp | 2418 static unsigned CCMaskForCondCode(ISD::CondCode CC) { in CCMaskForCondCode() 3001 SDValue Call, unsigned CCValid, uint64_t CC, in getIntrinsicCmp() 3180 static unsigned getVectorComparison(ISD::CondCode CC, CmpMode Mode) { in getVectorComparison() 3229 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, CmpMode Mode, in getVectorComparisonOrInvert() 3303 ISD::CondCode CC, in lowerVectorSETCC() 3383 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in lowerSETCC() local 3400 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(3))->get(); in lowerSTRICT_FSETCC() local 3418 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in lowerBR_CC() local 3458 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in lowerSELECT_CC() local 4820 SDValue CC = getCCResult(DAG, SDValue(Node, 0)); in lowerINTRINSIC_W_CHAIN() local
|
H A D | SystemZISelLowering.h | 446 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, in getRegisterTypeForCallingConv()
|