1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that Sparc uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "SparcISelLowering.h"
15 #include "MCTargetDesc/SparcMCExpr.h"
16 #include "MCTargetDesc/SparcMCTargetDesc.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "SparcRegisterInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "SparcTargetObjectFile.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/DiagnosticInfo.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Module.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/KnownBits.h"
37 using namespace llvm;
38
39
40 //===----------------------------------------------------------------------===//
41 // Calling Convention Implementation
42 //===----------------------------------------------------------------------===//
43
CC_Sparc_Assign_SRet(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)44 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
45 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags, CCState &State)
47 {
48 assert (ArgFlags.isSRet());
49
50 // Assign SRet argument.
51 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
52 0,
53 LocVT, LocInfo));
54 return true;
55 }
56
CC_Sparc_Assign_Split_64(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)57 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
58 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
59 ISD::ArgFlagsTy &ArgFlags, CCState &State)
60 {
61 static const MCPhysReg RegList[] = {
62 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
63 };
64 // Try to get first reg.
65 if (Register Reg = State.AllocateReg(RegList)) {
66 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
67 } else {
68 // Assign whole thing in stack.
69 State.addLoc(CCValAssign::getCustomMem(
70 ValNo, ValVT, State.AllocateStack(8, Align(4)), LocVT, LocInfo));
71 return true;
72 }
73
74 // Try to get second reg.
75 if (Register Reg = State.AllocateReg(RegList))
76 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
77 else
78 State.addLoc(CCValAssign::getCustomMem(
79 ValNo, ValVT, State.AllocateStack(4, Align(4)), LocVT, LocInfo));
80 return true;
81 }
82
CC_Sparc_Assign_Ret_Split_64(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)83 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
84 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags, CCState &State)
86 {
87 static const MCPhysReg RegList[] = {
88 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
89 };
90
91 // Try to get first reg.
92 if (Register Reg = State.AllocateReg(RegList))
93 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
94 else
95 return false;
96
97 // Try to get second reg.
98 if (Register Reg = State.AllocateReg(RegList))
99 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
100 else
101 return false;
102
103 return true;
104 }
105
106 // Allocate a full-sized argument for the 64-bit ABI.
Analyze_CC_Sparc64_Full(bool IsReturn,unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)107 static bool Analyze_CC_Sparc64_Full(bool IsReturn, unsigned &ValNo, MVT &ValVT,
108 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
109 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
110 assert((LocVT == MVT::f32 || LocVT == MVT::f128
111 || LocVT.getSizeInBits() == 64) &&
112 "Can't handle non-64 bits locations");
113
114 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
115 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
116 Align alignment = (LocVT == MVT::f128) ? Align(16) : Align(8);
117 unsigned Offset = State.AllocateStack(size, alignment);
118 unsigned Reg = 0;
119
120 if (LocVT == MVT::i64 && Offset < 6*8)
121 // Promote integers to %i0-%i5.
122 Reg = SP::I0 + Offset/8;
123 else if (LocVT == MVT::f64 && Offset < 16*8)
124 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
125 Reg = SP::D0 + Offset/8;
126 else if (LocVT == MVT::f32 && Offset < 16*8)
127 // Promote floats to %f1, %f3, ...
128 Reg = SP::F1 + Offset/4;
129 else if (LocVT == MVT::f128 && Offset < 16*8)
130 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
131 Reg = SP::Q0 + Offset/16;
132
133 // Promote to register when possible, otherwise use the stack slot.
134 if (Reg) {
135 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
136 return true;
137 }
138
139 // Bail out if this is a return CC and we run out of registers to place
140 // values into.
141 if (IsReturn)
142 return false;
143
144 // This argument goes on the stack in an 8-byte slot.
145 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
146 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
147 if (LocVT == MVT::f32)
148 Offset += 4;
149
150 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
151 return true;
152 }
153
154 // Allocate a half-sized argument for the 64-bit ABI.
155 //
156 // This is used when passing { float, int } structs by value in registers.
Analyze_CC_Sparc64_Half(bool IsReturn,unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)157 static bool Analyze_CC_Sparc64_Half(bool IsReturn, unsigned &ValNo, MVT &ValVT,
158 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
159 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
160 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
161 unsigned Offset = State.AllocateStack(4, Align(4));
162
163 if (LocVT == MVT::f32 && Offset < 16*8) {
164 // Promote floats to %f0-%f31.
165 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
166 LocVT, LocInfo));
167 return true;
168 }
169
170 if (LocVT == MVT::i32 && Offset < 6*8) {
171 // Promote integers to %i0-%i5, using half the register.
172 unsigned Reg = SP::I0 + Offset/8;
173 LocVT = MVT::i64;
174 LocInfo = CCValAssign::AExt;
175
176 // Set the Custom bit if this i32 goes in the high bits of a register.
177 if (Offset % 8 == 0)
178 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
179 LocVT, LocInfo));
180 else
181 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
182 return true;
183 }
184
185 // Bail out if this is a return CC and we run out of registers to place
186 // values into.
187 if (IsReturn)
188 return false;
189
190 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
191 return true;
192 }
193
CC_Sparc64_Full(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)194 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
195 CCValAssign::LocInfo &LocInfo,
196 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
197 return Analyze_CC_Sparc64_Full(false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
198 State);
199 }
200
CC_Sparc64_Half(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)201 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
202 CCValAssign::LocInfo &LocInfo,
203 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
204 return Analyze_CC_Sparc64_Half(false, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
205 State);
206 }
207
RetCC_Sparc64_Full(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)208 static bool RetCC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
209 CCValAssign::LocInfo &LocInfo,
210 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
211 return Analyze_CC_Sparc64_Full(true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
212 State);
213 }
214
RetCC_Sparc64_Half(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)215 static bool RetCC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
216 CCValAssign::LocInfo &LocInfo,
217 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
218 return Analyze_CC_Sparc64_Half(true, ValNo, ValVT, LocVT, LocInfo, ArgFlags,
219 State);
220 }
221
222 #include "SparcGenCallingConv.inc"
223
224 // The calling conventions in SparcCallingConv.td are described in terms of the
225 // callee's register window. This function translates registers to the
226 // corresponding caller window %o register.
toCallerWindow(unsigned Reg)227 static unsigned toCallerWindow(unsigned Reg) {
228 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
229 "Unexpected enum");
230 if (Reg >= SP::I0 && Reg <= SP::I7)
231 return Reg - SP::I0 + SP::O0;
232 return Reg;
233 }
234
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const235 bool SparcTargetLowering::CanLowerReturn(
236 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
237 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
238 SmallVector<CCValAssign, 16> RVLocs;
239 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
240 return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64
241 : RetCC_Sparc32);
242 }
243
244 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const245 SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
246 bool IsVarArg,
247 const SmallVectorImpl<ISD::OutputArg> &Outs,
248 const SmallVectorImpl<SDValue> &OutVals,
249 const SDLoc &DL, SelectionDAG &DAG) const {
250 if (Subtarget->is64Bit())
251 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
252 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
253 }
254
255 SDValue
LowerReturn_32(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const256 SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
257 bool IsVarArg,
258 const SmallVectorImpl<ISD::OutputArg> &Outs,
259 const SmallVectorImpl<SDValue> &OutVals,
260 const SDLoc &DL, SelectionDAG &DAG) const {
261 MachineFunction &MF = DAG.getMachineFunction();
262
263 // CCValAssign - represent the assignment of the return value to locations.
264 SmallVector<CCValAssign, 16> RVLocs;
265
266 // CCState - Info about the registers and stack slot.
267 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
268 *DAG.getContext());
269
270 // Analyze return values.
271 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
272
273 SDValue Glue;
274 SmallVector<SDValue, 4> RetOps(1, Chain);
275 // Make room for the return address offset.
276 RetOps.push_back(SDValue());
277
278 // Copy the result values into the output registers.
279 for (unsigned i = 0, realRVLocIdx = 0;
280 i != RVLocs.size();
281 ++i, ++realRVLocIdx) {
282 CCValAssign &VA = RVLocs[i];
283 assert(VA.isRegLoc() && "Can only return in registers!");
284
285 SDValue Arg = OutVals[realRVLocIdx];
286
287 if (VA.needsCustom()) {
288 assert(VA.getLocVT() == MVT::v2i32);
289 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
290 // happen by default if this wasn't a legal type)
291
292 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
293 Arg,
294 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
295 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
296 Arg,
297 DAG.getConstant(1, DL, getVectorIdxTy(DAG.getDataLayout())));
298
299 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Glue);
300 Glue = Chain.getValue(1);
301 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
302 VA = RVLocs[++i]; // skip ahead to next loc
303 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
304 Glue);
305 } else
306 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Glue);
307
308 // Guarantee that all emitted copies are stuck together with flags.
309 Glue = Chain.getValue(1);
310 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
311 }
312
313 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
314 // If the function returns a struct, copy the SRetReturnReg to I0
315 if (MF.getFunction().hasStructRetAttr()) {
316 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
317 Register Reg = SFI->getSRetReturnReg();
318 if (!Reg)
319 llvm_unreachable("sret virtual register not created in the entry block");
320 auto PtrVT = getPointerTy(DAG.getDataLayout());
321 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
322 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Glue);
323 Glue = Chain.getValue(1);
324 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
325 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
326 }
327
328 RetOps[0] = Chain; // Update chain.
329 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
330
331 // Add the glue if we have it.
332 if (Glue.getNode())
333 RetOps.push_back(Glue);
334
335 return DAG.getNode(SPISD::RET_GLUE, DL, MVT::Other, RetOps);
336 }
337
338 // Lower return values for the 64-bit ABI.
339 // Return values are passed the exactly the same way as function arguments.
340 SDValue
LowerReturn_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const341 SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
342 bool IsVarArg,
343 const SmallVectorImpl<ISD::OutputArg> &Outs,
344 const SmallVectorImpl<SDValue> &OutVals,
345 const SDLoc &DL, SelectionDAG &DAG) const {
346 // CCValAssign - represent the assignment of the return value to locations.
347 SmallVector<CCValAssign, 16> RVLocs;
348
349 // CCState - Info about the registers and stack slot.
350 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
351 *DAG.getContext());
352
353 // Analyze return values.
354 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
355
356 SDValue Glue;
357 SmallVector<SDValue, 4> RetOps(1, Chain);
358
359 // The second operand on the return instruction is the return address offset.
360 // The return address is always %i7+8 with the 64-bit ABI.
361 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
362
363 // Copy the result values into the output registers.
364 for (unsigned i = 0; i != RVLocs.size(); ++i) {
365 CCValAssign &VA = RVLocs[i];
366 assert(VA.isRegLoc() && "Can only return in registers!");
367 SDValue OutVal = OutVals[i];
368
369 // Integer return values must be sign or zero extended by the callee.
370 switch (VA.getLocInfo()) {
371 case CCValAssign::Full: break;
372 case CCValAssign::SExt:
373 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
374 break;
375 case CCValAssign::ZExt:
376 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
377 break;
378 case CCValAssign::AExt:
379 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
380 break;
381 default:
382 llvm_unreachable("Unknown loc info!");
383 }
384
385 // The custom bit on an i32 return value indicates that it should be passed
386 // in the high bits of the register.
387 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
388 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
389 DAG.getConstant(32, DL, MVT::i32));
390
391 // The next value may go in the low bits of the same register.
392 // Handle both at once.
393 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
394 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
395 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
396 // Skip the next value, it's already done.
397 ++i;
398 }
399 }
400
401 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Glue);
402
403 // Guarantee that all emitted copies are stuck together with flags.
404 Glue = Chain.getValue(1);
405 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
406 }
407
408 RetOps[0] = Chain; // Update chain.
409
410 // Add the flag if we have it.
411 if (Glue.getNode())
412 RetOps.push_back(Glue);
413
414 return DAG.getNode(SPISD::RET_GLUE, DL, MVT::Other, RetOps);
415 }
416
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const417 SDValue SparcTargetLowering::LowerFormalArguments(
418 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
419 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
420 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
421 if (Subtarget->is64Bit())
422 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
423 DL, DAG, InVals);
424 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
425 DL, DAG, InVals);
426 }
427
428 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
429 /// passed in either one or two GPRs, including FP values. TODO: we should
430 /// pass FP values in FP registers for fastcc functions.
LowerFormalArguments_32(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const431 SDValue SparcTargetLowering::LowerFormalArguments_32(
432 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
433 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
434 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
435 MachineFunction &MF = DAG.getMachineFunction();
436 MachineRegisterInfo &RegInfo = MF.getRegInfo();
437 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
438
439 // Assign locations to all of the incoming arguments.
440 SmallVector<CCValAssign, 16> ArgLocs;
441 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
442 *DAG.getContext());
443 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
444
445 const unsigned StackOffset = 92;
446 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
447
448 unsigned InIdx = 0;
449 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
450 CCValAssign &VA = ArgLocs[i];
451
452 if (Ins[InIdx].Flags.isSRet()) {
453 if (InIdx != 0)
454 report_fatal_error("sparc only supports sret on the first parameter");
455 // Get SRet from [%fp+64].
456 int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, 64, true);
457 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
458 SDValue Arg =
459 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
460 InVals.push_back(Arg);
461 continue;
462 }
463
464 if (VA.isRegLoc()) {
465 if (VA.needsCustom()) {
466 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
467
468 Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
469 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
470 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
471
472 assert(i+1 < e);
473 CCValAssign &NextVA = ArgLocs[++i];
474
475 SDValue LoVal;
476 if (NextVA.isMemLoc()) {
477 int FrameIdx = MF.getFrameInfo().
478 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
479 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
480 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
481 } else {
482 Register loReg = MF.addLiveIn(NextVA.getLocReg(),
483 &SP::IntRegsRegClass);
484 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
485 }
486
487 if (IsLittleEndian)
488 std::swap(LoVal, HiVal);
489
490 SDValue WholeValue =
491 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
492 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
493 InVals.push_back(WholeValue);
494 continue;
495 }
496 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
497 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
498 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
499 if (VA.getLocVT() == MVT::f32)
500 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
501 else if (VA.getLocVT() != MVT::i32) {
502 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
503 DAG.getValueType(VA.getLocVT()));
504 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
505 }
506 InVals.push_back(Arg);
507 continue;
508 }
509
510 assert(VA.isMemLoc());
511
512 unsigned Offset = VA.getLocMemOffset()+StackOffset;
513 auto PtrVT = getPointerTy(DAG.getDataLayout());
514
515 if (VA.needsCustom()) {
516 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
517 // If it is double-word aligned, just load.
518 if (Offset % 8 == 0) {
519 int FI = MF.getFrameInfo().CreateFixedObject(8,
520 Offset,
521 true);
522 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
523 SDValue Load =
524 DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
525 InVals.push_back(Load);
526 continue;
527 }
528
529 int FI = MF.getFrameInfo().CreateFixedObject(4,
530 Offset,
531 true);
532 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
533 SDValue HiVal =
534 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
535 int FI2 = MF.getFrameInfo().CreateFixedObject(4,
536 Offset+4,
537 true);
538 SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
539
540 SDValue LoVal =
541 DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, MachinePointerInfo());
542
543 if (IsLittleEndian)
544 std::swap(LoVal, HiVal);
545
546 SDValue WholeValue =
547 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
548 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
549 InVals.push_back(WholeValue);
550 continue;
551 }
552
553 int FI = MF.getFrameInfo().CreateFixedObject(4,
554 Offset,
555 true);
556 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
557 SDValue Load ;
558 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
559 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
560 } else if (VA.getValVT() == MVT::f128) {
561 report_fatal_error("SPARCv8 does not handle f128 in calls; "
562 "pass indirectly");
563 } else {
564 // We shouldn't see any other value types here.
565 llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
566 }
567 InVals.push_back(Load);
568 }
569
570 if (MF.getFunction().hasStructRetAttr()) {
571 // Copy the SRet Argument to SRetReturnReg.
572 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
573 Register Reg = SFI->getSRetReturnReg();
574 if (!Reg) {
575 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
576 SFI->setSRetReturnReg(Reg);
577 }
578 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
579 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
580 }
581
582 // Store remaining ArgRegs to the stack if this is a varargs function.
583 if (isVarArg) {
584 static const MCPhysReg ArgRegs[] = {
585 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
586 };
587 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
588 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
589 unsigned ArgOffset = CCInfo.getStackSize();
590 if (NumAllocated == 6)
591 ArgOffset += StackOffset;
592 else {
593 assert(!ArgOffset);
594 ArgOffset = 68+4*NumAllocated;
595 }
596
597 // Remember the vararg offset for the va_start implementation.
598 FuncInfo->setVarArgsFrameOffset(ArgOffset);
599
600 std::vector<SDValue> OutChains;
601
602 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
603 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
604 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
605 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
606
607 int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, ArgOffset,
608 true);
609 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
610
611 OutChains.push_back(
612 DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, MachinePointerInfo()));
613 ArgOffset += 4;
614 }
615
616 if (!OutChains.empty()) {
617 OutChains.push_back(Chain);
618 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
619 }
620 }
621
622 return Chain;
623 }
624
625 // Lower formal arguments for the 64 bit ABI.
LowerFormalArguments_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const626 SDValue SparcTargetLowering::LowerFormalArguments_64(
627 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
628 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
629 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
630 MachineFunction &MF = DAG.getMachineFunction();
631
632 // Analyze arguments according to CC_Sparc64.
633 SmallVector<CCValAssign, 16> ArgLocs;
634 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
635 *DAG.getContext());
636 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
637
638 // The argument array begins at %fp+BIAS+128, after the register save area.
639 const unsigned ArgArea = 128;
640
641 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
642 CCValAssign &VA = ArgLocs[i];
643 if (VA.isRegLoc()) {
644 // This argument is passed in a register.
645 // All integer register arguments are promoted by the caller to i64.
646
647 // Create a virtual register for the promoted live-in value.
648 Register VReg = MF.addLiveIn(VA.getLocReg(),
649 getRegClassFor(VA.getLocVT()));
650 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
651
652 // Get the high bits for i32 struct elements.
653 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
654 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
655 DAG.getConstant(32, DL, MVT::i32));
656
657 // The caller promoted the argument, so insert an Assert?ext SDNode so we
658 // won't promote the value again in this function.
659 switch (VA.getLocInfo()) {
660 case CCValAssign::SExt:
661 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
662 DAG.getValueType(VA.getValVT()));
663 break;
664 case CCValAssign::ZExt:
665 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
666 DAG.getValueType(VA.getValVT()));
667 break;
668 default:
669 break;
670 }
671
672 // Truncate the register down to the argument type.
673 if (VA.isExtInLoc())
674 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
675
676 InVals.push_back(Arg);
677 continue;
678 }
679
680 // The registers are exhausted. This argument was passed on the stack.
681 assert(VA.isMemLoc());
682 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
683 // beginning of the arguments area at %fp+BIAS+128.
684 unsigned Offset = VA.getLocMemOffset() + ArgArea;
685 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
686 // Adjust offset for extended arguments, SPARC is big-endian.
687 // The caller will have written the full slot with extended bytes, but we
688 // prefer our own extending loads.
689 if (VA.isExtInLoc())
690 Offset += 8 - ValSize;
691 int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);
692 InVals.push_back(
693 DAG.getLoad(VA.getValVT(), DL, Chain,
694 DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),
695 MachinePointerInfo::getFixedStack(MF, FI)));
696 }
697
698 if (!IsVarArg)
699 return Chain;
700
701 // This function takes variable arguments, some of which may have been passed
702 // in registers %i0-%i5. Variable floating point arguments are never passed
703 // in floating point registers. They go on %i0-%i5 or on the stack like
704 // integer arguments.
705 //
706 // The va_start intrinsic needs to know the offset to the first variable
707 // argument.
708 unsigned ArgOffset = CCInfo.getStackSize();
709 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
710 // Skip the 128 bytes of register save area.
711 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
712 Subtarget->getStackPointerBias());
713
714 // Save the variable arguments that were passed in registers.
715 // The caller is required to reserve stack space for 6 arguments regardless
716 // of how many arguments were actually passed.
717 SmallVector<SDValue, 8> OutChains;
718 for (; ArgOffset < 6*8; ArgOffset += 8) {
719 Register VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
720 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
721 int FI = MF.getFrameInfo().CreateFixedObject(8, ArgOffset + ArgArea, true);
722 auto PtrVT = getPointerTy(MF.getDataLayout());
723 OutChains.push_back(
724 DAG.getStore(Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
725 MachinePointerInfo::getFixedStack(MF, FI)));
726 }
727
728 if (!OutChains.empty())
729 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
730
731 return Chain;
732 }
733
734 // Check whether any of the argument registers are reserved
isAnyArgRegReserved(const SparcRegisterInfo * TRI,const MachineFunction & MF)735 static bool isAnyArgRegReserved(const SparcRegisterInfo *TRI,
736 const MachineFunction &MF) {
737 // The register window design means that outgoing parameters at O*
738 // will appear in the callee as I*.
739 // Be conservative and check both sides of the register names.
740 bool Outgoing =
741 llvm::any_of(SP::GPROutgoingArgRegClass, [TRI, &MF](MCPhysReg r) {
742 return TRI->isReservedReg(MF, r);
743 });
744 bool Incoming =
745 llvm::any_of(SP::GPRIncomingArgRegClass, [TRI, &MF](MCPhysReg r) {
746 return TRI->isReservedReg(MF, r);
747 });
748 return Outgoing || Incoming;
749 }
750
emitReservedArgRegCallError(const MachineFunction & MF)751 static void emitReservedArgRegCallError(const MachineFunction &MF) {
752 const Function &F = MF.getFunction();
753 F.getContext().diagnose(DiagnosticInfoUnsupported{
754 F, ("SPARC doesn't support"
755 " function calls if any of the argument registers is reserved.")});
756 }
757
758 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const759 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
760 SmallVectorImpl<SDValue> &InVals) const {
761 if (Subtarget->is64Bit())
762 return LowerCall_64(CLI, InVals);
763 return LowerCall_32(CLI, InVals);
764 }
765
hasReturnsTwiceAttr(SelectionDAG & DAG,SDValue Callee,const CallBase * Call)766 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
767 const CallBase *Call) {
768 if (Call)
769 return Call->hasFnAttr(Attribute::ReturnsTwice);
770
771 const Function *CalleeFn = nullptr;
772 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
773 CalleeFn = dyn_cast<Function>(G->getGlobal());
774 } else if (ExternalSymbolSDNode *E =
775 dyn_cast<ExternalSymbolSDNode>(Callee)) {
776 const Function &Fn = DAG.getMachineFunction().getFunction();
777 const Module *M = Fn.getParent();
778 const char *CalleeName = E->getSymbol();
779 CalleeFn = M->getFunction(CalleeName);
780 }
781
782 if (!CalleeFn)
783 return false;
784 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
785 }
786
787 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
788 /// for tail call optimization.
IsEligibleForTailCallOptimization(CCState & CCInfo,CallLoweringInfo & CLI,MachineFunction & MF) const789 bool SparcTargetLowering::IsEligibleForTailCallOptimization(
790 CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF) const {
791
792 auto &Outs = CLI.Outs;
793 auto &Caller = MF.getFunction();
794
795 // Do not tail call opt functions with "disable-tail-calls" attribute.
796 if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
797 return false;
798
799 // Do not tail call opt if the stack is used to pass parameters.
800 // 64-bit targets have a slightly higher limit since the ABI requires
801 // to allocate some space even when all the parameters fit inside registers.
802 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0;
803 if (CCInfo.getStackSize() > StackSizeLimit)
804 return false;
805
806 // Do not tail call opt if either the callee or caller returns
807 // a struct and the other does not.
808 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet())
809 return false;
810
811 // Byval parameters hand the function a pointer directly into the stack area
812 // we want to reuse during a tail call.
813 for (auto &Arg : Outs)
814 if (Arg.Flags.isByVal())
815 return false;
816
817 return true;
818 }
819
820 // Lower a call for the 32-bit ABI.
821 SDValue
LowerCall_32(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const822 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
823 SmallVectorImpl<SDValue> &InVals) const {
824 SelectionDAG &DAG = CLI.DAG;
825 SDLoc &dl = CLI.DL;
826 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
827 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
828 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
829 SDValue Chain = CLI.Chain;
830 SDValue Callee = CLI.Callee;
831 bool &isTailCall = CLI.IsTailCall;
832 CallingConv::ID CallConv = CLI.CallConv;
833 bool isVarArg = CLI.IsVarArg;
834 MachineFunction &MF = DAG.getMachineFunction();
835
836 // Analyze operands of the call, assigning locations to each operand.
837 SmallVector<CCValAssign, 16> ArgLocs;
838 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
839 *DAG.getContext());
840 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
841
842 isTailCall = isTailCall && IsEligibleForTailCallOptimization(
843 CCInfo, CLI, DAG.getMachineFunction());
844
845 // Get the size of the outgoing arguments stack space requirement.
846 unsigned ArgsSize = CCInfo.getStackSize();
847
848 // Keep stack frames 8-byte aligned.
849 ArgsSize = (ArgsSize+7) & ~7;
850
851 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
852
853 // Create local copies for byval args.
854 SmallVector<SDValue, 8> ByValArgs;
855 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
856 ISD::ArgFlagsTy Flags = Outs[i].Flags;
857 if (!Flags.isByVal())
858 continue;
859
860 SDValue Arg = OutVals[i];
861 unsigned Size = Flags.getByValSize();
862 Align Alignment = Flags.getNonZeroByValAlign();
863
864 if (Size > 0U) {
865 int FI = MFI.CreateStackObject(Size, Alignment, false);
866 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
867 SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
868
869 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Alignment,
870 false, // isVolatile,
871 (Size <= 32), // AlwaysInline if size <= 32,
872 false, // isTailCall
873 MachinePointerInfo(), MachinePointerInfo());
874 ByValArgs.push_back(FIPtr);
875 }
876 else {
877 SDValue nullVal;
878 ByValArgs.push_back(nullVal);
879 }
880 }
881
882 assert(!isTailCall || ArgsSize == 0);
883
884 if (!isTailCall)
885 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);
886
887 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
888 SmallVector<SDValue, 8> MemOpChains;
889
890 const unsigned StackOffset = 92;
891 bool hasStructRetAttr = false;
892 unsigned SRetArgSize = 0;
893 // Walk the register/memloc assignments, inserting copies/loads.
894 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
895 i != e;
896 ++i, ++realArgIdx) {
897 CCValAssign &VA = ArgLocs[i];
898 SDValue Arg = OutVals[realArgIdx];
899
900 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
901
902 // Use local copy if it is a byval arg.
903 if (Flags.isByVal()) {
904 Arg = ByValArgs[byvalArgIdx++];
905 if (!Arg) {
906 continue;
907 }
908 }
909
910 // Promote the value if needed.
911 switch (VA.getLocInfo()) {
912 default: llvm_unreachable("Unknown loc info!");
913 case CCValAssign::Full: break;
914 case CCValAssign::SExt:
915 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
916 break;
917 case CCValAssign::ZExt:
918 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
919 break;
920 case CCValAssign::AExt:
921 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
922 break;
923 case CCValAssign::BCvt:
924 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
925 break;
926 }
927
928 if (Flags.isSRet()) {
929 assert(VA.needsCustom());
930
931 if (isTailCall)
932 continue;
933
934 // store SRet argument in %sp+64
935 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
936 SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
937 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
938 MemOpChains.push_back(
939 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
940 hasStructRetAttr = true;
941 // sret only allowed on first argument
942 assert(Outs[realArgIdx].OrigArgIndex == 0);
943 SRetArgSize =
944 DAG.getDataLayout().getTypeAllocSize(CLI.getArgs()[0].IndirectType);
945 continue;
946 }
947
948 if (VA.needsCustom()) {
949 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
950
951 if (VA.isMemLoc()) {
952 unsigned Offset = VA.getLocMemOffset() + StackOffset;
953 // if it is double-word aligned, just store.
954 if (Offset % 8 == 0) {
955 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
956 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
957 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
958 MemOpChains.push_back(
959 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
960 continue;
961 }
962 }
963
964 if (VA.getLocVT() == MVT::f64) {
965 // Move from the float value from float registers into the
966 // integer registers.
967 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg))
968 Arg = bitcastConstantFPToInt(C, dl, DAG);
969 else
970 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
971 }
972
973 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
974 Arg,
975 DAG.getConstant(0, dl, getVectorIdxTy(DAG.getDataLayout())));
976 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
977 Arg,
978 DAG.getConstant(1, dl, getVectorIdxTy(DAG.getDataLayout())));
979
980 if (VA.isRegLoc()) {
981 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0));
982 assert(i+1 != e);
983 CCValAssign &NextVA = ArgLocs[++i];
984 if (NextVA.isRegLoc()) {
985 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
986 } else {
987 // Store the second part in stack.
988 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
989 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
990 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
991 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
992 MemOpChains.push_back(
993 DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
994 }
995 } else {
996 unsigned Offset = VA.getLocMemOffset() + StackOffset;
997 // Store the first part.
998 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
999 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
1000 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1001 MemOpChains.push_back(
1002 DAG.getStore(Chain, dl, Part0, PtrOff, MachinePointerInfo()));
1003 // Store the second part.
1004 PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
1005 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1006 MemOpChains.push_back(
1007 DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
1008 }
1009 continue;
1010 }
1011
1012 // Arguments that can be passed on register must be kept at
1013 // RegsToPass vector
1014 if (VA.isRegLoc()) {
1015 if (VA.getLocVT() != MVT::f32) {
1016 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1017 continue;
1018 }
1019 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
1020 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1021 continue;
1022 }
1023
1024 assert(VA.isMemLoc());
1025
1026 // Create a store off the stack pointer for this argument.
1027 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
1028 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset,
1029 dl);
1030 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
1031 MemOpChains.push_back(
1032 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
1033 }
1034
1035
1036 // Emit all stores, make sure the occur before any copies into physregs.
1037 if (!MemOpChains.empty())
1038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1039
1040 // Build a sequence of copy-to-reg nodes chained together with token
1041 // chain and flag operands which copy the outgoing args into registers.
1042 // The InGlue in necessary since all emitted instructions must be
1043 // stuck together.
1044 SDValue InGlue;
1045 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1046 Register Reg = RegsToPass[i].first;
1047 if (!isTailCall)
1048 Reg = toCallerWindow(Reg);
1049 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InGlue);
1050 InGlue = Chain.getValue(1);
1051 }
1052
1053 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB);
1054
1055 // If the callee is a GlobalAddress node (quite common, every direct call is)
1056 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1057 // Likewise ExternalSymbol -> TargetExternalSymbol.
1058 unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30
1059 : SparcMCExpr::VK_Sparc_WDISP30;
1060 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1061 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
1062 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1063 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
1064
1065 // Returns a chain & a flag for retval copy to use
1066 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1067 SmallVector<SDValue, 8> Ops;
1068 Ops.push_back(Chain);
1069 Ops.push_back(Callee);
1070 if (hasStructRetAttr)
1071 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
1072 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1073 Register Reg = RegsToPass[i].first;
1074 if (!isTailCall)
1075 Reg = toCallerWindow(Reg);
1076 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType()));
1077 }
1078
1079 // Add a register mask operand representing the call-preserved registers.
1080 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1081 const uint32_t *Mask =
1082 ((hasReturnsTwice)
1083 ? TRI->getRTCallPreservedMask(CallConv)
1084 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
1085
1086 if (isAnyArgRegReserved(TRI, MF))
1087 emitReservedArgRegCallError(MF);
1088
1089 assert(Mask && "Missing call preserved mask for calling convention");
1090 Ops.push_back(DAG.getRegisterMask(Mask));
1091
1092 if (InGlue.getNode())
1093 Ops.push_back(InGlue);
1094
1095 if (isTailCall) {
1096 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1097 return DAG.getNode(SPISD::TAIL_CALL, dl, MVT::Other, Ops);
1098 }
1099
1100 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
1101 InGlue = Chain.getValue(1);
1102
1103 Chain = DAG.getCALLSEQ_END(Chain, ArgsSize, 0, InGlue, dl);
1104 InGlue = Chain.getValue(1);
1105
1106 // Assign locations to each value returned by this call.
1107 SmallVector<CCValAssign, 16> RVLocs;
1108 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1109 *DAG.getContext());
1110
1111 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
1112
1113 // Copy all of the result registers out of their specified physreg.
1114 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1115 assert(RVLocs[i].isRegLoc() && "Can only return in registers!");
1116 if (RVLocs[i].getLocVT() == MVT::v2i32) {
1117 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
1118 SDValue Lo = DAG.getCopyFromReg(
1119 Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InGlue);
1120 Chain = Lo.getValue(1);
1121 InGlue = Lo.getValue(2);
1122 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
1123 DAG.getConstant(0, dl, MVT::i32));
1124 SDValue Hi = DAG.getCopyFromReg(
1125 Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InGlue);
1126 Chain = Hi.getValue(1);
1127 InGlue = Hi.getValue(2);
1128 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
1129 DAG.getConstant(1, dl, MVT::i32));
1130 InVals.push_back(Vec);
1131 } else {
1132 Chain =
1133 DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
1134 RVLocs[i].getValVT(), InGlue)
1135 .getValue(1);
1136 InGlue = Chain.getValue(2);
1137 InVals.push_back(Chain.getValue(0));
1138 }
1139 }
1140
1141 return Chain;
1142 }
1143
1144 // FIXME? Maybe this could be a TableGen attribute on some registers and
1145 // this table could be generated automatically from RegInfo.
getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const1146 Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
1147 const MachineFunction &MF) const {
1148 Register Reg = StringSwitch<Register>(RegName)
1149 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1150 .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
1151 .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)
1152 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7)
1153 .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3)
1154 .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7)
1155 .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
1156 .Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7", SP::G7)
1157 .Default(0);
1158
1159 // If we're directly referencing register names
1160 // (e.g in GCC C extension `register int r asm("g1");`),
1161 // make sure that said register is in the reserve list.
1162 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1163 if (!TRI->isReservedReg(MF, Reg))
1164 Reg = 0;
1165
1166 if (Reg)
1167 return Reg;
1168
1169 report_fatal_error("Invalid register name global variable");
1170 }
1171
1172 // Fixup floating point arguments in the ... part of a varargs call.
1173 //
1174 // The SPARC v9 ABI requires that floating point arguments are treated the same
1175 // as integers when calling a varargs function. This does not apply to the
1176 // fixed arguments that are part of the function's prototype.
1177 //
1178 // This function post-processes a CCValAssign array created by
1179 // AnalyzeCallOperands().
fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> & ArgLocs,ArrayRef<ISD::OutputArg> Outs)1180 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1181 ArrayRef<ISD::OutputArg> Outs) {
1182 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1183 CCValAssign &VA = ArgLocs[i];
1184 MVT ValTy = VA.getLocVT();
1185 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1186 // varargs functions.
1187 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1188 continue;
1189 // The fixed arguments to a varargs function still go in FP registers.
1190 if (Outs[VA.getValNo()].IsFixed)
1191 continue;
1192
1193 // This floating point argument should be reassigned.
1194 // Determine the offset into the argument array.
1195 Register firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1196 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1197 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1198 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1199
1200 if (Offset < 6*8) {
1201 // This argument should go in %i0-%i5.
1202 unsigned IReg = SP::I0 + Offset/8;
1203 if (ValTy == MVT::f64)
1204 // Full register, just bitconvert into i64.
1205 VA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), IReg, MVT::i64,
1206 CCValAssign::BCvt);
1207 else {
1208 assert(ValTy == MVT::f128 && "Unexpected type!");
1209 // Full register, just bitconvert into i128 -- We will lower this into
1210 // two i64s in LowerCall_64.
1211 VA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), IReg,
1212 MVT::i128, CCValAssign::BCvt);
1213 }
1214 } else {
1215 // This needs to go to memory, we're out of integer registers.
1216 VA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), Offset,
1217 VA.getLocVT(), VA.getLocInfo());
1218 }
1219 }
1220 }
1221
1222 // Lower a call for the 64-bit ABI.
1223 SDValue
LowerCall_64(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const1224 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1225 SmallVectorImpl<SDValue> &InVals) const {
1226 SelectionDAG &DAG = CLI.DAG;
1227 SDLoc DL = CLI.DL;
1228 SDValue Chain = CLI.Chain;
1229 auto PtrVT = getPointerTy(DAG.getDataLayout());
1230 MachineFunction &MF = DAG.getMachineFunction();
1231
1232 // Analyze operands of the call, assigning locations to each operand.
1233 SmallVector<CCValAssign, 16> ArgLocs;
1234 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1235 *DAG.getContext());
1236 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1237
1238 CLI.IsTailCall = CLI.IsTailCall && IsEligibleForTailCallOptimization(
1239 CCInfo, CLI, DAG.getMachineFunction());
1240
1241 // Get the size of the outgoing arguments stack space requirement.
1242 // The stack offset computed by CC_Sparc64 includes all arguments.
1243 // Called functions expect 6 argument words to exist in the stack frame, used
1244 // or not.
1245 unsigned StackReserved = 6 * 8u;
1246 unsigned ArgsSize = std::max<unsigned>(StackReserved, CCInfo.getStackSize());
1247
1248 // Keep stack frames 16-byte aligned.
1249 ArgsSize = alignTo(ArgsSize, 16);
1250
1251 // Varargs calls require special treatment.
1252 if (CLI.IsVarArg)
1253 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1254
1255 assert(!CLI.IsTailCall || ArgsSize == StackReserved);
1256
1257 // Adjust the stack pointer to make room for the arguments.
1258 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1259 // with more than 6 arguments.
1260 if (!CLI.IsTailCall)
1261 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
1262
1263 // Collect the set of registers to pass to the function and their values.
1264 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1265 // instruction.
1266 SmallVector<std::pair<Register, SDValue>, 8> RegsToPass;
1267
1268 // Collect chains from all the memory opeations that copy arguments to the
1269 // stack. They must follow the stack pointer adjustment above and precede the
1270 // call instruction itself.
1271 SmallVector<SDValue, 8> MemOpChains;
1272
1273 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1274 const CCValAssign &VA = ArgLocs[i];
1275 SDValue Arg = CLI.OutVals[i];
1276
1277 // Promote the value if needed.
1278 switch (VA.getLocInfo()) {
1279 default:
1280 llvm_unreachable("Unknown location info!");
1281 case CCValAssign::Full:
1282 break;
1283 case CCValAssign::SExt:
1284 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1285 break;
1286 case CCValAssign::ZExt:
1287 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1288 break;
1289 case CCValAssign::AExt:
1290 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1291 break;
1292 case CCValAssign::BCvt:
1293 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1294 // SPARC does not support i128 natively. Lower it into two i64, see below.
1295 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1296 || VA.getLocVT() != MVT::i128)
1297 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1298 break;
1299 }
1300
1301 if (VA.isRegLoc()) {
1302 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1303 && VA.getLocVT() == MVT::i128) {
1304 // Store and reload into the integer register reg and reg+1.
1305 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1306 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1307 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1308 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1309 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1310 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1311 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1312
1313 // Store to %sp+BIAS+128+Offset
1314 SDValue Store =
1315 DAG.getStore(Chain, DL, Arg, HiPtrOff, MachinePointerInfo());
1316 // Load into Reg and Reg+1
1317 SDValue Hi64 =
1318 DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, MachinePointerInfo());
1319 SDValue Lo64 =
1320 DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, MachinePointerInfo());
1321
1322 Register HiReg = VA.getLocReg();
1323 Register LoReg = VA.getLocReg() + 1;
1324 if (!CLI.IsTailCall) {
1325 HiReg = toCallerWindow(HiReg);
1326 LoReg = toCallerWindow(LoReg);
1327 }
1328
1329 RegsToPass.push_back(std::make_pair(HiReg, Hi64));
1330 RegsToPass.push_back(std::make_pair(LoReg, Lo64));
1331 continue;
1332 }
1333
1334 // The custom bit on an i32 return value indicates that it should be
1335 // passed in the high bits of the register.
1336 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1337 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1338 DAG.getConstant(32, DL, MVT::i32));
1339
1340 // The next value may go in the low bits of the same register.
1341 // Handle both at once.
1342 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1343 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1344 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1345 CLI.OutVals[i+1]);
1346 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1347 // Skip the next value, it's already done.
1348 ++i;
1349 }
1350 }
1351
1352 Register Reg = VA.getLocReg();
1353 if (!CLI.IsTailCall)
1354 Reg = toCallerWindow(Reg);
1355 RegsToPass.push_back(std::make_pair(Reg, Arg));
1356 continue;
1357 }
1358
1359 assert(VA.isMemLoc());
1360
1361 // Create a store off the stack pointer for this argument.
1362 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1363 // The argument area starts at %fp+BIAS+128 in the callee frame,
1364 // %sp+BIAS+128 in ours.
1365 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1366 Subtarget->getStackPointerBias() +
1367 128, DL);
1368 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1369 MemOpChains.push_back(
1370 DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
1371 }
1372
1373 // Emit all stores, make sure they occur before the call.
1374 if (!MemOpChains.empty())
1375 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1376
1377 // Build a sequence of CopyToReg nodes glued together with token chain and
1378 // glue operands which copy the outgoing args into registers. The InGlue is
1379 // necessary since all emitted instructions must be stuck together in order
1380 // to pass the live physical registers.
1381 SDValue InGlue;
1382 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1383 Chain = DAG.getCopyToReg(Chain, DL,
1384 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1385 InGlue = Chain.getValue(1);
1386 }
1387
1388 // If the callee is a GlobalAddress node (quite common, every direct call is)
1389 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1390 // Likewise ExternalSymbol -> TargetExternalSymbol.
1391 SDValue Callee = CLI.Callee;
1392 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CB);
1393 unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30
1394 : SparcMCExpr::VK_Sparc_WDISP30;
1395 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1396 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1397 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1398 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1399
1400 // Build the operands for the call instruction itself.
1401 SmallVector<SDValue, 8> Ops;
1402 Ops.push_back(Chain);
1403 Ops.push_back(Callee);
1404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1405 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1406 RegsToPass[i].second.getValueType()));
1407
1408 // Add a register mask operand representing the call-preserved registers.
1409 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1410 const uint32_t *Mask =
1411 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1412 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1413 CLI.CallConv));
1414
1415 if (isAnyArgRegReserved(TRI, MF))
1416 emitReservedArgRegCallError(MF);
1417
1418 assert(Mask && "Missing call preserved mask for calling convention");
1419 Ops.push_back(DAG.getRegisterMask(Mask));
1420
1421 // Make sure the CopyToReg nodes are glued to the call instruction which
1422 // consumes the registers.
1423 if (InGlue.getNode())
1424 Ops.push_back(InGlue);
1425
1426 // Now the call itself.
1427 if (CLI.IsTailCall) {
1428 DAG.getMachineFunction().getFrameInfo().setHasTailCall();
1429 return DAG.getNode(SPISD::TAIL_CALL, DL, MVT::Other, Ops);
1430 }
1431 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1432 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1433 InGlue = Chain.getValue(1);
1434
1435 // Revert the stack pointer immediately after the call.
1436 Chain = DAG.getCALLSEQ_END(Chain, ArgsSize, 0, InGlue, DL);
1437 InGlue = Chain.getValue(1);
1438
1439 // Now extract the return values. This is more or less the same as
1440 // LowerFormalArguments_64.
1441
1442 // Assign locations to each value returned by this call.
1443 SmallVector<CCValAssign, 16> RVLocs;
1444 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1445 *DAG.getContext());
1446
1447 // Set inreg flag manually for codegen generated library calls that
1448 // return float.
1449 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CB)
1450 CLI.Ins[0].Flags.setInReg();
1451
1452 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1453
1454 // Copy all of the result registers out of their specified physreg.
1455 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1456 CCValAssign &VA = RVLocs[i];
1457 assert(VA.isRegLoc() && "Can only return in registers!");
1458 unsigned Reg = toCallerWindow(VA.getLocReg());
1459
1460 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1461 // reside in the same register in the high and low bits. Reuse the
1462 // CopyFromReg previous node to avoid duplicate copies.
1463 SDValue RV;
1464 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1465 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1466 RV = Chain.getValue(0);
1467
1468 // But usually we'll create a new CopyFromReg for a different register.
1469 if (!RV.getNode()) {
1470 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1471 Chain = RV.getValue(1);
1472 InGlue = Chain.getValue(2);
1473 }
1474
1475 // Get the high bits for i32 struct elements.
1476 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1477 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1478 DAG.getConstant(32, DL, MVT::i32));
1479
1480 // The callee promoted the return value, so insert an Assert?ext SDNode so
1481 // we won't promote the value again in this function.
1482 switch (VA.getLocInfo()) {
1483 case CCValAssign::SExt:
1484 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1485 DAG.getValueType(VA.getValVT()));
1486 break;
1487 case CCValAssign::ZExt:
1488 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1489 DAG.getValueType(VA.getValVT()));
1490 break;
1491 default:
1492 break;
1493 }
1494
1495 // Truncate the register down to the return value type.
1496 if (VA.isExtInLoc())
1497 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1498
1499 InVals.push_back(RV);
1500 }
1501
1502 return Chain;
1503 }
1504
1505 //===----------------------------------------------------------------------===//
1506 // TargetLowering Implementation
1507 //===----------------------------------------------------------------------===//
1508
shouldExpandAtomicRMWInIR(AtomicRMWInst * AI) const1509 TargetLowering::AtomicExpansionKind SparcTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
1510 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1511 AI->getType()->getPrimitiveSizeInBits() == 32)
1512 return AtomicExpansionKind::None; // Uses xchg instruction
1513
1514 return AtomicExpansionKind::CmpXChg;
1515 }
1516
1517 /// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1518 /// rcond condition.
intCondCCodeToRcond(ISD::CondCode CC)1519 static SPCC::CondCodes intCondCCodeToRcond(ISD::CondCode CC) {
1520 switch (CC) {
1521 default:
1522 llvm_unreachable("Unknown/unsigned integer condition code!");
1523 case ISD::SETEQ:
1524 return SPCC::REG_Z;
1525 case ISD::SETNE:
1526 return SPCC::REG_NZ;
1527 case ISD::SETLT:
1528 return SPCC::REG_LZ;
1529 case ISD::SETGT:
1530 return SPCC::REG_GZ;
1531 case ISD::SETLE:
1532 return SPCC::REG_LEZ;
1533 case ISD::SETGE:
1534 return SPCC::REG_GEZ;
1535 }
1536 }
1537
1538 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1539 /// condition.
IntCondCCodeToICC(ISD::CondCode CC)1540 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1541 switch (CC) {
1542 default: llvm_unreachable("Unknown integer condition code!");
1543 case ISD::SETEQ: return SPCC::ICC_E;
1544 case ISD::SETNE: return SPCC::ICC_NE;
1545 case ISD::SETLT: return SPCC::ICC_L;
1546 case ISD::SETGT: return SPCC::ICC_G;
1547 case ISD::SETLE: return SPCC::ICC_LE;
1548 case ISD::SETGE: return SPCC::ICC_GE;
1549 case ISD::SETULT: return SPCC::ICC_CS;
1550 case ISD::SETULE: return SPCC::ICC_LEU;
1551 case ISD::SETUGT: return SPCC::ICC_GU;
1552 case ISD::SETUGE: return SPCC::ICC_CC;
1553 }
1554 }
1555
1556 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1557 /// FCC condition.
FPCondCCodeToFCC(ISD::CondCode CC)1558 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1559 switch (CC) {
1560 default: llvm_unreachable("Unknown fp condition code!");
1561 case ISD::SETEQ:
1562 case ISD::SETOEQ: return SPCC::FCC_E;
1563 case ISD::SETNE:
1564 case ISD::SETUNE: return SPCC::FCC_NE;
1565 case ISD::SETLT:
1566 case ISD::SETOLT: return SPCC::FCC_L;
1567 case ISD::SETGT:
1568 case ISD::SETOGT: return SPCC::FCC_G;
1569 case ISD::SETLE:
1570 case ISD::SETOLE: return SPCC::FCC_LE;
1571 case ISD::SETGE:
1572 case ISD::SETOGE: return SPCC::FCC_GE;
1573 case ISD::SETULT: return SPCC::FCC_UL;
1574 case ISD::SETULE: return SPCC::FCC_ULE;
1575 case ISD::SETUGT: return SPCC::FCC_UG;
1576 case ISD::SETUGE: return SPCC::FCC_UGE;
1577 case ISD::SETUO: return SPCC::FCC_U;
1578 case ISD::SETO: return SPCC::FCC_O;
1579 case ISD::SETONE: return SPCC::FCC_LG;
1580 case ISD::SETUEQ: return SPCC::FCC_UE;
1581 }
1582 }
1583
SparcTargetLowering(const TargetMachine & TM,const SparcSubtarget & STI)1584 SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1585 const SparcSubtarget &STI)
1586 : TargetLowering(TM), Subtarget(&STI) {
1587 MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
1588
1589 // Instructions which use registers as conditionals examine all the
1590 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1591 // matters much whether it's ZeroOrOneBooleanContent, or
1592 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1593 // former.
1594 setBooleanContents(ZeroOrOneBooleanContent);
1595 setBooleanVectorContents(ZeroOrOneBooleanContent);
1596
1597 // Set up the register classes.
1598 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1599 if (!Subtarget->useSoftFloat()) {
1600 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1601 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1602 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1603 }
1604 if (Subtarget->is64Bit()) {
1605 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1606 } else {
1607 // On 32bit sparc, we define a double-register 32bit register
1608 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1609 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1610
1611 // ...but almost all operations must be expanded, so set that as
1612 // the default.
1613 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1614 setOperationAction(Op, MVT::v2i32, Expand);
1615 }
1616 // Truncating/extending stores/loads are also not supported.
1617 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1618 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand);
1619 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1620 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand);
1621
1622 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand);
1623 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
1624 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand);
1625
1626 setTruncStoreAction(VT, MVT::v2i32, Expand);
1627 setTruncStoreAction(MVT::v2i32, VT, Expand);
1628 }
1629 // However, load and store *are* legal.
1630 setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
1631 setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1632 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
1633 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
1634
1635 // And we need to promote i64 loads/stores into vector load/store
1636 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1637 setOperationAction(ISD::STORE, MVT::i64, Custom);
1638
1639 // Sadly, this doesn't work:
1640 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1641 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1642 }
1643
1644 // Turn FP extload into load/fpextend
1645 for (MVT VT : MVT::fp_valuetypes()) {
1646 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1647 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1648 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1649 }
1650
1651 // Sparc doesn't have i1 sign extending load
1652 for (MVT VT : MVT::integer_valuetypes())
1653 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1654
1655 // Turn FP truncstore into trunc + store.
1656 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1657 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1658 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1659 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
1660 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1661 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1662
1663 // Custom legalize GlobalAddress nodes into LO/HI parts.
1664 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
1665 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
1666 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
1667 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
1668
1669 // Sparc doesn't have sext_inreg, replace them with shl/sra
1670 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1671 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1672 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1673
1674 // Sparc has no REM or DIVREM operations.
1675 setOperationAction(ISD::UREM, MVT::i32, Expand);
1676 setOperationAction(ISD::SREM, MVT::i32, Expand);
1677 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1678 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1679
1680 // ... nor does SparcV9.
1681 if (Subtarget->is64Bit()) {
1682 setOperationAction(ISD::UREM, MVT::i64, Expand);
1683 setOperationAction(ISD::SREM, MVT::i64, Expand);
1684 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1685 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1686 }
1687
1688 // Custom expand fp<->sint
1689 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1690 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1691 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1692 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1693
1694 // Custom Expand fp<->uint
1695 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1696 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1697 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1698 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1699
1700 // Lower f16 conversion operations into library calls
1701 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
1702 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
1703 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
1704 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
1705 setOperationAction(ISD::FP16_TO_FP, MVT::f128, Expand);
1706 setOperationAction(ISD::FP_TO_FP16, MVT::f128, Expand);
1707
1708 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1709 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1710
1711 // Sparc has no select or setcc: expand to SELECT_CC.
1712 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1713 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1714 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1715 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1716
1717 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1718 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1719 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1720 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1721
1722 // Sparc doesn't have BRCOND either, it has BR_CC.
1723 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1724 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1725 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1726 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1727 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1728 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1729 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1730
1731 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1732 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1733 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1734 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1735
1736 setOperationAction(ISD::ADDC, MVT::i32, Custom);
1737 setOperationAction(ISD::ADDE, MVT::i32, Custom);
1738 setOperationAction(ISD::SUBC, MVT::i32, Custom);
1739 setOperationAction(ISD::SUBE, MVT::i32, Custom);
1740
1741 if (Subtarget->is64Bit()) {
1742 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1743 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1744 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1745 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1746 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1747 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1748 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1749 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1750 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1751 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1752
1753 setOperationAction(ISD::CTPOP, MVT::i64,
1754 Subtarget->usePopc() ? Legal : Expand);
1755 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1756 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1757 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1758 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1759 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1760 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1761 }
1762
1763 // ATOMICs.
1764 // Atomics are supported on SparcV9. 32-bit atomics are also
1765 // supported by some Leon SparcV8 variants. Otherwise, atomics
1766 // are unsupported.
1767 if (Subtarget->isV9())
1768 setMaxAtomicSizeInBitsSupported(64);
1769 else if (Subtarget->hasLeonCasa())
1770 setMaxAtomicSizeInBitsSupported(32);
1771 else
1772 setMaxAtomicSizeInBitsSupported(0);
1773
1774 setMinCmpXchgSizeInBits(32);
1775
1776 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1777
1778 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1779
1780 // Custom Lower Atomic LOAD/STORE
1781 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1782 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1783
1784 if (Subtarget->is64Bit()) {
1785 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1786 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1787 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1788 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1789 }
1790
1791 if (!Subtarget->is64Bit()) {
1792 // These libcalls are not available in 32-bit.
1793 setLibcallName(RTLIB::MULO_I64, nullptr);
1794 setLibcallName(RTLIB::MUL_I128, nullptr);
1795 setLibcallName(RTLIB::SHL_I128, nullptr);
1796 setLibcallName(RTLIB::SRL_I128, nullptr);
1797 setLibcallName(RTLIB::SRA_I128, nullptr);
1798 }
1799
1800 setLibcallName(RTLIB::MULO_I128, nullptr);
1801
1802 if (!Subtarget->isV9()) {
1803 // SparcV8 does not have FNEGD and FABSD.
1804 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1805 setOperationAction(ISD::FABS, MVT::f64, Custom);
1806 }
1807
1808 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1809 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1810 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1811 setOperationAction(ISD::FREM , MVT::f128, Expand);
1812 setOperationAction(ISD::FMA , MVT::f128, Expand);
1813 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1814 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1815 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1816 setOperationAction(ISD::FREM , MVT::f64, Expand);
1817 setOperationAction(ISD::FMA , MVT::f64, Expand);
1818 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1819 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1820 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1821 setOperationAction(ISD::FREM , MVT::f32, Expand);
1822 setOperationAction(ISD::FMA , MVT::f32, Expand);
1823 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1824 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1825 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1826 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1827 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1828 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1829 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1830 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1831 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1832 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1833 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1834
1835 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1836 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1837 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1838
1839 // Expands to [SU]MUL_LOHI.
1840 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1841 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1842 setOperationAction(ISD::MUL, MVT::i32, Expand);
1843
1844 if (Subtarget->useSoftMulDiv()) {
1845 // .umul works for both signed and unsigned
1846 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1847 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1848 setLibcallName(RTLIB::MUL_I32, ".umul");
1849
1850 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1851 setLibcallName(RTLIB::SDIV_I32, ".div");
1852
1853 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1854 setLibcallName(RTLIB::UDIV_I32, ".udiv");
1855
1856 setLibcallName(RTLIB::SREM_I32, ".rem");
1857 setLibcallName(RTLIB::UREM_I32, ".urem");
1858 }
1859
1860 if (Subtarget->is64Bit()) {
1861 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1862 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1863 setOperationAction(ISD::MULHU, MVT::i64, Expand);
1864 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1865
1866 setOperationAction(ISD::UMULO, MVT::i64, Custom);
1867 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1868
1869 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1870 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1871 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1872 }
1873
1874 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1875 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1876 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1877 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1878
1879 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1880 setOperationAction(ISD::DEBUGTRAP , MVT::Other, Legal);
1881
1882 // Use the default implementation.
1883 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1884 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1885 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1886 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1887 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1888
1889 setStackPointerRegisterToSaveRestore(SP::O6);
1890
1891 setOperationAction(ISD::CTPOP, MVT::i32,
1892 Subtarget->usePopc() ? Legal : Expand);
1893
1894 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1895 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1896 setOperationAction(ISD::STORE, MVT::f128, Legal);
1897 } else {
1898 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1899 setOperationAction(ISD::STORE, MVT::f128, Custom);
1900 }
1901
1902 if (Subtarget->hasHardQuad()) {
1903 setOperationAction(ISD::FADD, MVT::f128, Legal);
1904 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1905 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1906 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1907 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1908 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1909 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1910 if (Subtarget->isV9()) {
1911 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1912 setOperationAction(ISD::FABS, MVT::f128, Legal);
1913 } else {
1914 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1915 setOperationAction(ISD::FABS, MVT::f128, Custom);
1916 }
1917
1918 if (!Subtarget->is64Bit()) {
1919 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1920 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1921 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1922 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1923 }
1924
1925 } else {
1926 // Custom legalize f128 operations.
1927
1928 setOperationAction(ISD::FADD, MVT::f128, Custom);
1929 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1930 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1931 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1932 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1933 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1934 setOperationAction(ISD::FABS, MVT::f128, Custom);
1935
1936 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1937 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1938 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1939
1940 // Setup Runtime library names.
1941 if (Subtarget->is64Bit() && !Subtarget->useSoftFloat()) {
1942 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1943 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1944 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1945 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1946 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1947 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1948 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1949 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1950 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1951 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1952 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1953 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1954 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1955 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1956 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1957 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1958 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1959 } else if (!Subtarget->useSoftFloat()) {
1960 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1961 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1962 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1963 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1964 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1965 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1966 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1967 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1968 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1969 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1970 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1971 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1972 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1973 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1974 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1975 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1976 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1977 }
1978 }
1979
1980 if (Subtarget->fixAllFDIVSQRT()) {
1981 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1982 // the former instructions generate errata on LEON processors.
1983 setOperationAction(ISD::FDIV, MVT::f32, Promote);
1984 setOperationAction(ISD::FSQRT, MVT::f32, Promote);
1985 }
1986
1987 if (Subtarget->hasNoFMULS()) {
1988 setOperationAction(ISD::FMUL, MVT::f32, Promote);
1989 }
1990
1991 // Custom combine bitcast between f64 and v2i32
1992 if (!Subtarget->is64Bit())
1993 setTargetDAGCombine(ISD::BITCAST);
1994
1995 if (Subtarget->hasLeonCycleCounter())
1996 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1997
1998 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1999
2000 setMinFunctionAlignment(Align(4));
2001
2002 computeRegisterProperties(Subtarget->getRegisterInfo());
2003 }
2004
useSoftFloat() const2005 bool SparcTargetLowering::useSoftFloat() const {
2006 return Subtarget->useSoftFloat();
2007 }
2008
getTargetNodeName(unsigned Opcode) const2009 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
2010 switch ((SPISD::NodeType)Opcode) {
2011 case SPISD::FIRST_NUMBER: break;
2012 case SPISD::CMPICC: return "SPISD::CMPICC";
2013 case SPISD::CMPFCC: return "SPISD::CMPFCC";
2014 case SPISD::CMPFCC_V9:
2015 return "SPISD::CMPFCC_V9";
2016 case SPISD::BRICC: return "SPISD::BRICC";
2017 case SPISD::BPICC:
2018 return "SPISD::BPICC";
2019 case SPISD::BPXCC:
2020 return "SPISD::BPXCC";
2021 case SPISD::BRFCC: return "SPISD::BRFCC";
2022 case SPISD::BRFCC_V9:
2023 return "SPISD::BRFCC_V9";
2024 case SPISD::BR_REG:
2025 return "SPISD::BR_REG";
2026 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
2027 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
2028 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
2029 case SPISD::SELECT_REG:
2030 return "SPISD::SELECT_REG";
2031 case SPISD::Hi: return "SPISD::Hi";
2032 case SPISD::Lo: return "SPISD::Lo";
2033 case SPISD::FTOI: return "SPISD::FTOI";
2034 case SPISD::ITOF: return "SPISD::ITOF";
2035 case SPISD::FTOX: return "SPISD::FTOX";
2036 case SPISD::XTOF: return "SPISD::XTOF";
2037 case SPISD::CALL: return "SPISD::CALL";
2038 case SPISD::RET_GLUE: return "SPISD::RET_GLUE";
2039 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
2040 case SPISD::FLUSHW: return "SPISD::FLUSHW";
2041 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
2042 case SPISD::TLS_LD: return "SPISD::TLS_LD";
2043 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
2044 case SPISD::TAIL_CALL: return "SPISD::TAIL_CALL";
2045 case SPISD::LOAD_GDOP: return "SPISD::LOAD_GDOP";
2046 }
2047 return nullptr;
2048 }
2049
getSetCCResultType(const DataLayout &,LLVMContext &,EVT VT) const2050 EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
2051 EVT VT) const {
2052 if (!VT.isVector())
2053 return MVT::i32;
2054 return VT.changeVectorElementTypeToInteger();
2055 }
2056
2057 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2058 /// be zero. Op is expected to be a target specific node. Used by DAG
2059 /// combiner.
computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const2060 void SparcTargetLowering::computeKnownBitsForTargetNode
2061 (const SDValue Op,
2062 KnownBits &Known,
2063 const APInt &DemandedElts,
2064 const SelectionDAG &DAG,
2065 unsigned Depth) const {
2066 KnownBits Known2;
2067 Known.resetAll();
2068
2069 switch (Op.getOpcode()) {
2070 default: break;
2071 case SPISD::SELECT_ICC:
2072 case SPISD::SELECT_XCC:
2073 case SPISD::SELECT_FCC:
2074 Known = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
2075 Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
2076
2077 // Only known if known in both the LHS and RHS.
2078 Known = Known.intersectWith(Known2);
2079 break;
2080 }
2081 }
2082
2083 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
2084 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
LookThroughSetCC(SDValue & LHS,SDValue & RHS,ISD::CondCode CC,unsigned & SPCC)2085 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
2086 ISD::CondCode CC, unsigned &SPCC) {
2087 if (isNullConstant(RHS) && CC == ISD::SETNE &&
2088 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
2089 LHS.getOpcode() == SPISD::SELECT_XCC) &&
2090 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
2091 (LHS.getOpcode() == SPISD::SELECT_FCC &&
2092 (LHS.getOperand(3).getOpcode() == SPISD::CMPFCC ||
2093 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC_V9))) &&
2094 isOneConstant(LHS.getOperand(0)) && isNullConstant(LHS.getOperand(1))) {
2095 SDValue CMPCC = LHS.getOperand(3);
2096 SPCC = LHS.getConstantOperandVal(2);
2097 LHS = CMPCC.getOperand(0);
2098 RHS = CMPCC.getOperand(1);
2099 }
2100 }
2101
2102 // Convert to a target node and set target flags.
withTargetFlags(SDValue Op,unsigned TF,SelectionDAG & DAG) const2103 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
2104 SelectionDAG &DAG) const {
2105 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
2106 return DAG.getTargetGlobalAddress(GA->getGlobal(),
2107 SDLoc(GA),
2108 GA->getValueType(0),
2109 GA->getOffset(), TF);
2110
2111 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
2112 return DAG.getTargetConstantPool(CP->getConstVal(), CP->getValueType(0),
2113 CP->getAlign(), CP->getOffset(), TF);
2114
2115 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
2116 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
2117 Op.getValueType(),
2118 0,
2119 TF);
2120
2121 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
2122 return DAG.getTargetExternalSymbol(ES->getSymbol(),
2123 ES->getValueType(0), TF);
2124
2125 llvm_unreachable("Unhandled address SDNode");
2126 }
2127
2128 // Split Op into high and low parts according to HiTF and LoTF.
2129 // Return an ADD node combining the parts.
makeHiLoPair(SDValue Op,unsigned HiTF,unsigned LoTF,SelectionDAG & DAG) const2130 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
2131 unsigned HiTF, unsigned LoTF,
2132 SelectionDAG &DAG) const {
2133 SDLoc DL(Op);
2134 EVT VT = Op.getValueType();
2135 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
2136 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
2137 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
2138 }
2139
2140 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
2141 // or ExternalSymbol SDNode.
makeAddress(SDValue Op,SelectionDAG & DAG) const2142 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
2143 SDLoc DL(Op);
2144 EVT VT = getPointerTy(DAG.getDataLayout());
2145
2146 // Handle PIC mode first. SPARC needs a got load for every variable!
2147 if (isPositionIndependent()) {
2148 const Module *M = DAG.getMachineFunction().getFunction().getParent();
2149 PICLevel::Level picLevel = M->getPICLevel();
2150 SDValue Idx;
2151
2152 if (picLevel == PICLevel::SmallPIC) {
2153 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
2154 Idx = DAG.getNode(SPISD::Lo, DL, Op.getValueType(),
2155 withTargetFlags(Op, SparcMCExpr::VK_Sparc_GOT13, DAG));
2156 } else {
2157 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
2158 Idx = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
2159 SparcMCExpr::VK_Sparc_GOT10, DAG);
2160 }
2161
2162 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
2163 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx);
2164 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2165 // function has calls.
2166 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2167 MFI.setHasCalls(true);
2168 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
2169 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
2170 }
2171
2172 // This is one of the absolute code models.
2173 switch(getTargetMachine().getCodeModel()) {
2174 default:
2175 llvm_unreachable("Unsupported absolute code model");
2176 case CodeModel::Small:
2177 // abs32.
2178 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
2179 SparcMCExpr::VK_Sparc_LO, DAG);
2180 case CodeModel::Medium: {
2181 // abs44.
2182 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
2183 SparcMCExpr::VK_Sparc_M44, DAG);
2184 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
2185 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
2186 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
2187 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
2188 }
2189 case CodeModel::Large: {
2190 // abs64.
2191 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
2192 SparcMCExpr::VK_Sparc_HM, DAG);
2193 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
2194 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
2195 SparcMCExpr::VK_Sparc_LO, DAG);
2196 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
2197 }
2198 }
2199 }
2200
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const2201 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2202 SelectionDAG &DAG) const {
2203 return makeAddress(Op, DAG);
2204 }
2205
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const2206 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2207 SelectionDAG &DAG) const {
2208 return makeAddress(Op, DAG);
2209 }
2210
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const2211 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2212 SelectionDAG &DAG) const {
2213 return makeAddress(Op, DAG);
2214 }
2215
LowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const2216 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2217 SelectionDAG &DAG) const {
2218
2219 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2220 if (DAG.getTarget().useEmulatedTLS())
2221 return LowerToTLSEmulatedModel(GA, DAG);
2222
2223 SDLoc DL(GA);
2224 const GlobalValue *GV = GA->getGlobal();
2225 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2226
2227 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2228
2229 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2230 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
2231 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
2232 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
2233 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
2234 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
2235 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
2236 unsigned addTF = ((model == TLSModel::GeneralDynamic)
2237 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
2238 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
2239 unsigned callTF = ((model == TLSModel::GeneralDynamic)
2240 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
2241 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
2242
2243 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2244 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2245 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
2246 withTargetFlags(Op, addTF, DAG));
2247
2248 SDValue Chain = DAG.getEntryNode();
2249 SDValue InGlue;
2250
2251 Chain = DAG.getCALLSEQ_START(Chain, 1, 0, DL);
2252 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InGlue);
2253 InGlue = Chain.getValue(1);
2254 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
2255 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
2256
2257 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2258 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2259 DAG.getMachineFunction(), CallingConv::C);
2260 assert(Mask && "Missing call preserved mask for calling convention");
2261 SDValue Ops[] = {Chain,
2262 Callee,
2263 Symbol,
2264 DAG.getRegister(SP::O0, PtrVT),
2265 DAG.getRegisterMask(Mask),
2266 InGlue};
2267 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2268 InGlue = Chain.getValue(1);
2269 Chain = DAG.getCALLSEQ_END(Chain, 1, 0, InGlue, DL);
2270 InGlue = Chain.getValue(1);
2271 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InGlue);
2272
2273 if (model != TLSModel::LocalDynamic)
2274 return Ret;
2275
2276 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2277 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
2278 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2279 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
2280 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2281 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
2282 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
2283 }
2284
2285 if (model == TLSModel::InitialExec) {
2286 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
2287 : SparcMCExpr::VK_Sparc_TLS_IE_LD);
2288
2289 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2290
2291 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2292 // function has calls.
2293 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2294 MFI.setHasCalls(true);
2295
2296 SDValue TGA = makeHiLoPair(Op,
2297 SparcMCExpr::VK_Sparc_TLS_IE_HI22,
2298 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
2299 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
2300 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
2301 DL, PtrVT, Ptr,
2302 withTargetFlags(Op, ldTF, DAG));
2303 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
2304 DAG.getRegister(SP::G7, PtrVT), Offset,
2305 withTargetFlags(Op,
2306 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
2307 }
2308
2309 assert(model == TLSModel::LocalExec);
2310 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2311 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
2312 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2313 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
2314 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2315
2316 return DAG.getNode(ISD::ADD, DL, PtrVT,
2317 DAG.getRegister(SP::G7, PtrVT), Offset);
2318 }
2319
LowerF128_LibCallArg(SDValue Chain,ArgListTy & Args,SDValue Arg,const SDLoc & DL,SelectionDAG & DAG) const2320 SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2321 ArgListTy &Args, SDValue Arg,
2322 const SDLoc &DL,
2323 SelectionDAG &DAG) const {
2324 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2325 EVT ArgVT = Arg.getValueType();
2326 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2327
2328 ArgListEntry Entry;
2329 Entry.Node = Arg;
2330 Entry.Ty = ArgTy;
2331
2332 if (ArgTy->isFP128Ty()) {
2333 // Create a stack object and pass the pointer to the library function.
2334 int FI = MFI.CreateStackObject(16, Align(8), false);
2335 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2336 Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(),
2337 Align(8));
2338
2339 Entry.Node = FIPtr;
2340 Entry.Ty = PointerType::getUnqual(ArgTy);
2341 }
2342 Args.push_back(Entry);
2343 return Chain;
2344 }
2345
2346 SDValue
LowerF128Op(SDValue Op,SelectionDAG & DAG,const char * LibFuncName,unsigned numArgs) const2347 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2348 const char *LibFuncName,
2349 unsigned numArgs) const {
2350
2351 ArgListTy Args;
2352
2353 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2354 auto PtrVT = getPointerTy(DAG.getDataLayout());
2355
2356 SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2357 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2358 Type *RetTyABI = RetTy;
2359 SDValue Chain = DAG.getEntryNode();
2360 SDValue RetPtr;
2361
2362 if (RetTy->isFP128Ty()) {
2363 // Create a Stack Object to receive the return value of type f128.
2364 ArgListEntry Entry;
2365 int RetFI = MFI.CreateStackObject(16, Align(8), false);
2366 RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2367 Entry.Node = RetPtr;
2368 Entry.Ty = PointerType::getUnqual(RetTy);
2369 if (!Subtarget->is64Bit()) {
2370 Entry.IsSRet = true;
2371 Entry.IndirectType = RetTy;
2372 }
2373 Entry.IsReturned = false;
2374 Args.push_back(Entry);
2375 RetTyABI = Type::getVoidTy(*DAG.getContext());
2376 }
2377
2378 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2379 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2380 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2381 }
2382 TargetLowering::CallLoweringInfo CLI(DAG);
2383 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2384 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args));
2385
2386 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2387
2388 // chain is in second result.
2389 if (RetTyABI == RetTy)
2390 return CallInfo.first;
2391
2392 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2393
2394 Chain = CallInfo.second;
2395
2396 // Load RetPtr to get the return value.
2397 return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
2398 MachinePointerInfo(), Align(8));
2399 }
2400
LowerF128Compare(SDValue LHS,SDValue RHS,unsigned & SPCC,const SDLoc & DL,SelectionDAG & DAG) const2401 SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2402 unsigned &SPCC, const SDLoc &DL,
2403 SelectionDAG &DAG) const {
2404
2405 const char *LibCall = nullptr;
2406 bool is64Bit = Subtarget->is64Bit();
2407 switch(SPCC) {
2408 default: llvm_unreachable("Unhandled conditional code!");
2409 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2410 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2411 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2412 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2413 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2414 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2415 case SPCC::FCC_UL :
2416 case SPCC::FCC_ULE:
2417 case SPCC::FCC_UG :
2418 case SPCC::FCC_UGE:
2419 case SPCC::FCC_U :
2420 case SPCC::FCC_O :
2421 case SPCC::FCC_LG :
2422 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2423 }
2424
2425 auto PtrVT = getPointerTy(DAG.getDataLayout());
2426 SDValue Callee = DAG.getExternalSymbol(LibCall, PtrVT);
2427 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2428 ArgListTy Args;
2429 SDValue Chain = DAG.getEntryNode();
2430 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2431 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2432
2433 TargetLowering::CallLoweringInfo CLI(DAG);
2434 CLI.setDebugLoc(DL).setChain(Chain)
2435 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args));
2436
2437 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2438
2439 // result is in first, and chain is in second result.
2440 SDValue Result = CallInfo.first;
2441
2442 switch(SPCC) {
2443 default: {
2444 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2445 SPCC = SPCC::ICC_NE;
2446 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2447 }
2448 case SPCC::FCC_UL : {
2449 SDValue Mask = DAG.getConstant(1, DL, Result.getValueType());
2450 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2451 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2452 SPCC = SPCC::ICC_NE;
2453 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2454 }
2455 case SPCC::FCC_ULE: {
2456 SDValue RHS = DAG.getConstant(2, DL, Result.getValueType());
2457 SPCC = SPCC::ICC_NE;
2458 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2459 }
2460 case SPCC::FCC_UG : {
2461 SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
2462 SPCC = SPCC::ICC_G;
2463 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2464 }
2465 case SPCC::FCC_UGE: {
2466 SDValue RHS = DAG.getConstant(1, DL, Result.getValueType());
2467 SPCC = SPCC::ICC_NE;
2468 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2469 }
2470
2471 case SPCC::FCC_U : {
2472 SDValue RHS = DAG.getConstant(3, DL, Result.getValueType());
2473 SPCC = SPCC::ICC_E;
2474 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2475 }
2476 case SPCC::FCC_O : {
2477 SDValue RHS = DAG.getConstant(3, DL, Result.getValueType());
2478 SPCC = SPCC::ICC_NE;
2479 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2480 }
2481 case SPCC::FCC_LG : {
2482 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType());
2483 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2484 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2485 SPCC = SPCC::ICC_NE;
2486 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2487 }
2488 case SPCC::FCC_UE : {
2489 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType());
2490 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2491 SDValue RHS = DAG.getConstant(0, DL, Result.getValueType());
2492 SPCC = SPCC::ICC_E;
2493 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2494 }
2495 }
2496 }
2497
2498 static SDValue
LowerF128_FPEXTEND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2499 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2500 const SparcTargetLowering &TLI) {
2501
2502 if (Op.getOperand(0).getValueType() == MVT::f64)
2503 return TLI.LowerF128Op(Op, DAG,
2504 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2505
2506 if (Op.getOperand(0).getValueType() == MVT::f32)
2507 return TLI.LowerF128Op(Op, DAG,
2508 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2509
2510 llvm_unreachable("fpextend with non-float operand!");
2511 return SDValue();
2512 }
2513
2514 static SDValue
LowerF128_FPROUND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2515 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2516 const SparcTargetLowering &TLI) {
2517 // FP_ROUND on f64 and f32 are legal.
2518 if (Op.getOperand(0).getValueType() != MVT::f128)
2519 return Op;
2520
2521 if (Op.getValueType() == MVT::f64)
2522 return TLI.LowerF128Op(Op, DAG,
2523 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2524 if (Op.getValueType() == MVT::f32)
2525 return TLI.LowerF128Op(Op, DAG,
2526 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2527
2528 llvm_unreachable("fpround to non-float!");
2529 return SDValue();
2530 }
2531
LowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2532 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2533 const SparcTargetLowering &TLI,
2534 bool hasHardQuad) {
2535 SDLoc dl(Op);
2536 EVT VT = Op.getValueType();
2537 assert(VT == MVT::i32 || VT == MVT::i64);
2538
2539 // Expand f128 operations to fp128 abi calls.
2540 if (Op.getOperand(0).getValueType() == MVT::f128
2541 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2542 const char *libName = TLI.getLibcallName(VT == MVT::i32
2543 ? RTLIB::FPTOSINT_F128_I32
2544 : RTLIB::FPTOSINT_F128_I64);
2545 return TLI.LowerF128Op(Op, DAG, libName, 1);
2546 }
2547
2548 // Expand if the resulting type is illegal.
2549 if (!TLI.isTypeLegal(VT))
2550 return SDValue();
2551
2552 // Otherwise, Convert the fp value to integer in an FP register.
2553 if (VT == MVT::i32)
2554 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2555 else
2556 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2557
2558 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2559 }
2560
LowerSINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2561 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2562 const SparcTargetLowering &TLI,
2563 bool hasHardQuad) {
2564 SDLoc dl(Op);
2565 EVT OpVT = Op.getOperand(0).getValueType();
2566 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2567
2568 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2569
2570 // Expand f128 operations to fp128 ABI calls.
2571 if (Op.getValueType() == MVT::f128
2572 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2573 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2574 ? RTLIB::SINTTOFP_I32_F128
2575 : RTLIB::SINTTOFP_I64_F128);
2576 return TLI.LowerF128Op(Op, DAG, libName, 1);
2577 }
2578
2579 // Expand if the operand type is illegal.
2580 if (!TLI.isTypeLegal(OpVT))
2581 return SDValue();
2582
2583 // Otherwise, Convert the int value to FP in an FP register.
2584 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2585 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2586 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2587 }
2588
LowerFP_TO_UINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2589 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2590 const SparcTargetLowering &TLI,
2591 bool hasHardQuad) {
2592 SDLoc dl(Op);
2593 EVT VT = Op.getValueType();
2594
2595 // Expand if it does not involve f128 or the target has support for
2596 // quad floating point instructions and the resulting type is legal.
2597 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2598 (hasHardQuad && TLI.isTypeLegal(VT)))
2599 return SDValue();
2600
2601 assert(VT == MVT::i32 || VT == MVT::i64);
2602
2603 return TLI.LowerF128Op(Op, DAG,
2604 TLI.getLibcallName(VT == MVT::i32
2605 ? RTLIB::FPTOUINT_F128_I32
2606 : RTLIB::FPTOUINT_F128_I64),
2607 1);
2608 }
2609
LowerUINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2610 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2611 const SparcTargetLowering &TLI,
2612 bool hasHardQuad) {
2613 SDLoc dl(Op);
2614 EVT OpVT = Op.getOperand(0).getValueType();
2615 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2616
2617 // Expand if it does not involve f128 or the target has support for
2618 // quad floating point instructions and the operand type is legal.
2619 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2620 return SDValue();
2621
2622 return TLI.LowerF128Op(Op, DAG,
2623 TLI.getLibcallName(OpVT == MVT::i32
2624 ? RTLIB::UINTTOFP_I32_F128
2625 : RTLIB::UINTTOFP_I64_F128),
2626 1);
2627 }
2628
LowerBR_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad,bool isV9,bool is64Bit)2629 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2630 const SparcTargetLowering &TLI, bool hasHardQuad,
2631 bool isV9, bool is64Bit) {
2632 SDValue Chain = Op.getOperand(0);
2633 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2634 SDValue LHS = Op.getOperand(2);
2635 SDValue RHS = Op.getOperand(3);
2636 SDValue Dest = Op.getOperand(4);
2637 SDLoc dl(Op);
2638 unsigned Opc, SPCC = ~0U;
2639
2640 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2641 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2642 LookThroughSetCC(LHS, RHS, CC, SPCC);
2643 assert(LHS.getValueType() == RHS.getValueType());
2644
2645 // Get the condition flag.
2646 SDValue CompareFlag;
2647 if (LHS.getValueType().isInteger()) {
2648 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2649 // and the RHS is zero we might be able to use a specialized branch.
2650 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2651 isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC))
2652 return DAG.getNode(SPISD::BR_REG, dl, MVT::Other, Chain, Dest,
2653 DAG.getConstant(intCondCCodeToRcond(CC), dl, MVT::i32),
2654 LHS);
2655
2656 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2657 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2658 if (isV9)
2659 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2660 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BPICC : SPISD::BPXCC;
2661 else
2662 // Non-v9 targets don't have xcc.
2663 Opc = SPISD::BRICC;
2664 } else {
2665 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2666 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2667 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2668 Opc = isV9 ? SPISD::BPICC : SPISD::BRICC;
2669 } else {
2670 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2671 CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
2672 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2673 Opc = isV9 ? SPISD::BRFCC_V9 : SPISD::BRFCC;
2674 }
2675 }
2676 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2677 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2678 }
2679
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad,bool isV9,bool is64Bit)2680 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2681 const SparcTargetLowering &TLI, bool hasHardQuad,
2682 bool isV9, bool is64Bit) {
2683 SDValue LHS = Op.getOperand(0);
2684 SDValue RHS = Op.getOperand(1);
2685 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2686 SDValue TrueVal = Op.getOperand(2);
2687 SDValue FalseVal = Op.getOperand(3);
2688 SDLoc dl(Op);
2689 unsigned Opc, SPCC = ~0U;
2690
2691 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2692 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2693 LookThroughSetCC(LHS, RHS, CC, SPCC);
2694 assert(LHS.getValueType() == RHS.getValueType());
2695
2696 SDValue CompareFlag;
2697 if (LHS.getValueType().isInteger()) {
2698 // On V9 processors running in 64-bit mode, if CC compares two `i64`s
2699 // and the RHS is zero we might be able to use a specialized select.
2700 // All SELECT_CC between any two scalar integer types are eligible for
2701 // lowering to specialized instructions. Additionally, f32 and f64 types
2702 // are also eligible, but for f128 we can only use the specialized
2703 // instruction when we have hardquad.
2704 EVT ValType = TrueVal.getValueType();
2705 bool IsEligibleType = ValType.isScalarInteger() || ValType == MVT::f32 ||
2706 ValType == MVT::f64 ||
2707 (ValType == MVT::f128 && hasHardQuad);
2708 if (is64Bit && isV9 && LHS.getValueType() == MVT::i64 &&
2709 isNullConstant(RHS) && !ISD::isUnsignedIntSetCC(CC) && IsEligibleType)
2710 return DAG.getNode(
2711 SPISD::SELECT_REG, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2712 DAG.getConstant(intCondCCodeToRcond(CC), dl, MVT::i32), LHS);
2713
2714 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2715 Opc = LHS.getValueType() == MVT::i32 ?
2716 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2717 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2718 } else {
2719 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2720 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2721 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2722 Opc = SPISD::SELECT_ICC;
2723 } else {
2724 unsigned CmpOpc = isV9 ? SPISD::CMPFCC_V9 : SPISD::CMPFCC;
2725 CompareFlag = DAG.getNode(CmpOpc, dl, MVT::Glue, LHS, RHS);
2726 Opc = SPISD::SELECT_FCC;
2727 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2728 }
2729 }
2730 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2731 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2732 }
2733
LowerVASTART(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2734 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2735 const SparcTargetLowering &TLI) {
2736 MachineFunction &MF = DAG.getMachineFunction();
2737 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2738 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2739
2740 // Need frame address to find the address of VarArgsFrameIndex.
2741 MF.getFrameInfo().setFrameAddressIsTaken(true);
2742
2743 // vastart just stores the address of the VarArgsFrameIndex slot into the
2744 // memory location argument.
2745 SDLoc DL(Op);
2746 SDValue Offset =
2747 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2748 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2749 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2750 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2751 MachinePointerInfo(SV));
2752 }
2753
LowerVAARG(SDValue Op,SelectionDAG & DAG)2754 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2755 SDNode *Node = Op.getNode();
2756 EVT VT = Node->getValueType(0);
2757 SDValue InChain = Node->getOperand(0);
2758 SDValue VAListPtr = Node->getOperand(1);
2759 EVT PtrVT = VAListPtr.getValueType();
2760 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2761 SDLoc DL(Node);
2762 SDValue VAList =
2763 DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
2764 // Increment the pointer, VAList, to the next vaarg.
2765 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2766 DAG.getIntPtrConstant(VT.getSizeInBits()/8,
2767 DL));
2768 // Store the incremented VAList to the legalized pointer.
2769 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, VAListPtr,
2770 MachinePointerInfo(SV));
2771 // Load the actual argument out of the pointer VAList.
2772 // We can't count on greater alignment than the word size.
2773 return DAG.getLoad(
2774 VT, DL, InChain, VAList, MachinePointerInfo(),
2775 Align(std::min(PtrVT.getFixedSizeInBits(), VT.getFixedSizeInBits()) / 8));
2776 }
2777
LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2778 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2779 const SparcSubtarget *Subtarget) {
2780 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2781 SDValue Size = Op.getOperand(1); // Legalize the size.
2782 MaybeAlign Alignment =
2783 cast<ConstantSDNode>(Op.getOperand(2))->getMaybeAlignValue();
2784 Align StackAlign = Subtarget->getFrameLowering()->getStackAlign();
2785 EVT VT = Size->getValueType(0);
2786 SDLoc dl(Op);
2787
2788 // TODO: implement over-aligned alloca. (Note: also implies
2789 // supporting support for overaligned function frames + dynamic
2790 // allocations, at all, which currently isn't supported)
2791 if (Alignment && *Alignment > StackAlign) {
2792 const MachineFunction &MF = DAG.getMachineFunction();
2793 report_fatal_error("Function \"" + Twine(MF.getName()) + "\": "
2794 "over-aligned dynamic alloca not supported.");
2795 }
2796
2797 // The resultant pointer needs to be above the register spill area
2798 // at the bottom of the stack.
2799 unsigned regSpillArea;
2800 if (Subtarget->is64Bit()) {
2801 regSpillArea = 128;
2802 } else {
2803 // On Sparc32, the size of the spill area is 92. Unfortunately,
2804 // that's only 4-byte aligned, not 8-byte aligned (the stack
2805 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2806 // aligned dynamic allocation, we actually need to add 96 to the
2807 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2808
2809 // That also means adding 4 to the size of the allocation --
2810 // before applying the 8-byte rounding. Unfortunately, we the
2811 // value we get here has already had rounding applied. So, we need
2812 // to add 8, instead, wasting a bit more memory.
2813
2814 // Further, this only actually needs to be done if the required
2815 // alignment is > 4, but, we've lost that info by this point, too,
2816 // so we always apply it.
2817
2818 // (An alternative approach would be to always reserve 96 bytes
2819 // instead of the required 92, but then we'd waste 4 extra bytes
2820 // in every frame, not just those with dynamic stack allocations)
2821
2822 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2823
2824 Size = DAG.getNode(ISD::ADD, dl, VT, Size,
2825 DAG.getConstant(8, dl, VT));
2826 regSpillArea = 96;
2827 }
2828
2829 unsigned SPReg = SP::O6;
2830 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2831 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2832 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2833
2834 regSpillArea += Subtarget->getStackPointerBias();
2835
2836 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2837 DAG.getConstant(regSpillArea, dl, VT));
2838 SDValue Ops[2] = { NewVal, Chain };
2839 return DAG.getMergeValues(Ops, dl);
2840 }
2841
2842
getFLUSHW(SDValue Op,SelectionDAG & DAG)2843 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2844 SDLoc dl(Op);
2845 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2846 dl, MVT::Other, DAG.getEntryNode());
2847 return Chain;
2848 }
2849
getFRAMEADDR(uint64_t depth,SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget,bool AlwaysFlush=false)2850 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2851 const SparcSubtarget *Subtarget,
2852 bool AlwaysFlush = false) {
2853 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2854 MFI.setFrameAddressIsTaken(true);
2855
2856 EVT VT = Op.getValueType();
2857 SDLoc dl(Op);
2858 unsigned FrameReg = SP::I6;
2859 unsigned stackBias = Subtarget->getStackPointerBias();
2860
2861 SDValue FrameAddr;
2862 SDValue Chain;
2863
2864 // flush first to make sure the windowed registers' values are in stack
2865 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2866
2867 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2868
2869 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2870
2871 while (depth--) {
2872 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2873 DAG.getIntPtrConstant(Offset, dl));
2874 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo());
2875 }
2876 if (Subtarget->is64Bit())
2877 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2878 DAG.getIntPtrConstant(stackBias, dl));
2879 return FrameAddr;
2880 }
2881
2882
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2883 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2884 const SparcSubtarget *Subtarget) {
2885
2886 uint64_t depth = Op.getConstantOperandVal(0);
2887
2888 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2889
2890 }
2891
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,const SparcSubtarget * Subtarget)2892 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2893 const SparcTargetLowering &TLI,
2894 const SparcSubtarget *Subtarget) {
2895 MachineFunction &MF = DAG.getMachineFunction();
2896 MachineFrameInfo &MFI = MF.getFrameInfo();
2897 MFI.setReturnAddressIsTaken(true);
2898
2899 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2900 return SDValue();
2901
2902 EVT VT = Op.getValueType();
2903 SDLoc dl(Op);
2904 uint64_t depth = Op.getConstantOperandVal(0);
2905
2906 SDValue RetAddr;
2907 if (depth == 0) {
2908 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2909 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2910 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2911 return RetAddr;
2912 }
2913
2914 // Need frame address to find return address of the caller.
2915 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget, true);
2916
2917 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2918 SDValue Ptr = DAG.getNode(ISD::ADD,
2919 dl, VT,
2920 FrameAddr,
2921 DAG.getIntPtrConstant(Offset, dl));
2922 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2923
2924 return RetAddr;
2925 }
2926
LowerF64Op(SDValue SrcReg64,const SDLoc & dl,SelectionDAG & DAG,unsigned opcode)2927 static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2928 unsigned opcode) {
2929 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2930 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2931
2932 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2933 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2934 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2935
2936 // Note: in little-endian, the floating-point value is stored in the
2937 // registers are in the opposite order, so the subreg with the sign
2938 // bit is the highest-numbered (odd), rather than the
2939 // lowest-numbered (even).
2940
2941 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2942 SrcReg64);
2943 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2944 SrcReg64);
2945
2946 if (DAG.getDataLayout().isLittleEndian())
2947 Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32);
2948 else
2949 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2950
2951 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2952 dl, MVT::f64), 0);
2953 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2954 DstReg64, Hi32);
2955 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2956 DstReg64, Lo32);
2957 return DstReg64;
2958 }
2959
2960 // Lower a f128 load into two f64 loads.
LowerF128Load(SDValue Op,SelectionDAG & DAG)2961 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2962 {
2963 SDLoc dl(Op);
2964 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2965 assert(LdNode->getOffset().isUndef() && "Unexpected node type");
2966
2967 Align Alignment = commonAlignment(LdNode->getOriginalAlign(), 8);
2968
2969 SDValue Hi64 =
2970 DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(),
2971 LdNode->getPointerInfo(), Alignment);
2972 EVT addrVT = LdNode->getBasePtr().getValueType();
2973 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2974 LdNode->getBasePtr(),
2975 DAG.getConstant(8, dl, addrVT));
2976 SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr,
2977 LdNode->getPointerInfo().getWithOffset(8),
2978 Alignment);
2979
2980 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2981 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2982
2983 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2984 dl, MVT::f128);
2985 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2986 MVT::f128,
2987 SDValue(InFP128, 0),
2988 Hi64,
2989 SubRegEven);
2990 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2991 MVT::f128,
2992 SDValue(InFP128, 0),
2993 Lo64,
2994 SubRegOdd);
2995 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2996 SDValue(Lo64.getNode(), 1) };
2997 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2998 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2999 return DAG.getMergeValues(Ops, dl);
3000 }
3001
LowerLOAD(SDValue Op,SelectionDAG & DAG)3002 static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
3003 {
3004 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
3005
3006 EVT MemVT = LdNode->getMemoryVT();
3007 if (MemVT == MVT::f128)
3008 return LowerF128Load(Op, DAG);
3009
3010 return Op;
3011 }
3012
3013 // Lower a f128 store into two f64 stores.
LowerF128Store(SDValue Op,SelectionDAG & DAG)3014 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
3015 SDLoc dl(Op);
3016 StoreSDNode *StNode = cast<StoreSDNode>(Op.getNode());
3017 assert(StNode->getOffset().isUndef() && "Unexpected node type");
3018
3019 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
3020 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
3021
3022 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3023 dl,
3024 MVT::f64,
3025 StNode->getValue(),
3026 SubRegEven);
3027 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3028 dl,
3029 MVT::f64,
3030 StNode->getValue(),
3031 SubRegOdd);
3032
3033 Align Alignment = commonAlignment(StNode->getOriginalAlign(), 8);
3034
3035 SDValue OutChains[2];
3036 OutChains[0] =
3037 DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0),
3038 StNode->getBasePtr(), StNode->getPointerInfo(),
3039 Alignment);
3040 EVT addrVT = StNode->getBasePtr().getValueType();
3041 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
3042 StNode->getBasePtr(),
3043 DAG.getConstant(8, dl, addrVT));
3044 OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), LoPtr,
3045 StNode->getPointerInfo().getWithOffset(8),
3046 Alignment);
3047 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
3048 }
3049
LowerSTORE(SDValue Op,SelectionDAG & DAG)3050 static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
3051 {
3052 SDLoc dl(Op);
3053 StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
3054
3055 EVT MemVT = St->getMemoryVT();
3056 if (MemVT == MVT::f128)
3057 return LowerF128Store(Op, DAG);
3058
3059 if (MemVT == MVT::i64) {
3060 // Custom handling for i64 stores: turn it into a bitcast and a
3061 // v2i32 store.
3062 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
3063 SDValue Chain = DAG.getStore(
3064 St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
3065 St->getOriginalAlign(), St->getMemOperand()->getFlags(),
3066 St->getAAInfo());
3067 return Chain;
3068 }
3069
3070 return SDValue();
3071 }
3072
LowerFNEGorFABS(SDValue Op,SelectionDAG & DAG,bool isV9)3073 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
3074 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
3075 && "invalid opcode");
3076
3077 SDLoc dl(Op);
3078
3079 if (Op.getValueType() == MVT::f64)
3080 return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
3081 if (Op.getValueType() != MVT::f128)
3082 return Op;
3083
3084 // Lower fabs/fneg on f128 to fabs/fneg on f64
3085 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
3086 // (As with LowerF64Op, on little-endian, we need to negate the odd
3087 // subreg)
3088
3089 SDValue SrcReg128 = Op.getOperand(0);
3090 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
3091 SrcReg128);
3092 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
3093 SrcReg128);
3094
3095 if (DAG.getDataLayout().isLittleEndian()) {
3096 if (isV9)
3097 Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
3098 else
3099 Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
3100 } else {
3101 if (isV9)
3102 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
3103 else
3104 Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
3105 }
3106
3107 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
3108 dl, MVT::f128), 0);
3109 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
3110 DstReg128, Hi64);
3111 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
3112 DstReg128, Lo64);
3113 return DstReg128;
3114 }
3115
LowerADDC_ADDE_SUBC_SUBE(SDValue Op,SelectionDAG & DAG)3116 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
3117
3118 if (Op.getValueType() != MVT::i64)
3119 return Op;
3120
3121 SDLoc dl(Op);
3122 SDValue Src1 = Op.getOperand(0);
3123 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
3124 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
3125 DAG.getConstant(32, dl, MVT::i64));
3126 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
3127
3128 SDValue Src2 = Op.getOperand(1);
3129 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
3130 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
3131 DAG.getConstant(32, dl, MVT::i64));
3132 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
3133
3134
3135 bool hasChain = false;
3136 unsigned hiOpc = Op.getOpcode();
3137 switch (Op.getOpcode()) {
3138 default: llvm_unreachable("Invalid opcode");
3139 case ISD::ADDC: hiOpc = ISD::ADDE; break;
3140 case ISD::ADDE: hasChain = true; break;
3141 case ISD::SUBC: hiOpc = ISD::SUBE; break;
3142 case ISD::SUBE: hasChain = true; break;
3143 }
3144 SDValue Lo;
3145 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
3146 if (hasChain) {
3147 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
3148 Op.getOperand(2));
3149 } else {
3150 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
3151 }
3152 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
3153 SDValue Carry = Hi.getValue(1);
3154
3155 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
3156 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
3157 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
3158 DAG.getConstant(32, dl, MVT::i64));
3159
3160 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
3161 SDValue Ops[2] = { Dst, Carry };
3162 return DAG.getMergeValues(Ops, dl);
3163 }
3164
3165 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
3166 // in LegalizeDAG.cpp except the order of arguments to the library function.
LowerUMULO_SMULO(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)3167 static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
3168 const SparcTargetLowering &TLI)
3169 {
3170 unsigned opcode = Op.getOpcode();
3171 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
3172
3173 bool isSigned = (opcode == ISD::SMULO);
3174 EVT VT = MVT::i64;
3175 EVT WideVT = MVT::i128;
3176 SDLoc dl(Op);
3177 SDValue LHS = Op.getOperand(0);
3178
3179 if (LHS.getValueType() != VT)
3180 return Op;
3181
3182 SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
3183
3184 SDValue RHS = Op.getOperand(1);
3185 SDValue HiLHS, HiRHS;
3186 if (isSigned) {
3187 HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
3188 HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
3189 } else {
3190 HiLHS = DAG.getConstant(0, dl, VT);
3191 HiRHS = DAG.getConstant(0, dl, MVT::i64);
3192 }
3193
3194 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
3195
3196 TargetLowering::MakeLibCallOptions CallOptions;
3197 CallOptions.setSExt(isSigned);
3198 SDValue MulResult = TLI.makeLibCall(DAG,
3199 RTLIB::MUL_I128, WideVT,
3200 Args, CallOptions, dl).first;
3201 SDValue BottomHalf, TopHalf;
3202 std::tie(BottomHalf, TopHalf) = DAG.SplitScalar(MulResult, dl, VT, VT);
3203 if (isSigned) {
3204 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
3205 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
3206 } else {
3207 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
3208 ISD::SETNE);
3209 }
3210 // MulResult is a node with an illegal type. Because such things are not
3211 // generally permitted during this phase of legalization, ensure that
3212 // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
3213 // been folded.
3214 assert(MulResult->use_empty() && "Illegally typed node still in use!");
3215
3216 SDValue Ops[2] = { BottomHalf, TopHalf } ;
3217 return DAG.getMergeValues(Ops, dl);
3218 }
3219
LowerATOMIC_LOAD_STORE(SDValue Op,SelectionDAG & DAG)3220 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
3221 if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getSuccessOrdering())) {
3222 // Expand with a fence.
3223 return SDValue();
3224 }
3225
3226 // Monotonic load/stores are legal.
3227 return Op;
3228 }
3229
LowerINTRINSIC_WO_CHAIN(SDValue Op,SelectionDAG & DAG) const3230 SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3231 SelectionDAG &DAG) const {
3232 unsigned IntNo = Op.getConstantOperandVal(0);
3233 SDLoc dl(Op);
3234 switch (IntNo) {
3235 default: return SDValue(); // Don't custom lower most intrinsics.
3236 case Intrinsic::thread_pointer: {
3237 EVT PtrVT = getPointerTy(DAG.getDataLayout());
3238 return DAG.getRegister(SP::G7, PtrVT);
3239 }
3240 }
3241 }
3242
3243 SDValue SparcTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const3244 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3245
3246 bool hasHardQuad = Subtarget->hasHardQuad();
3247 bool isV9 = Subtarget->isV9();
3248 bool is64Bit = Subtarget->is64Bit();
3249
3250 switch (Op.getOpcode()) {
3251 default: llvm_unreachable("Should not custom lower this!");
3252
3253 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
3254 Subtarget);
3255 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3256 Subtarget);
3257 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3258 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3259 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3260 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3261 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
3262 hasHardQuad);
3263 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
3264 hasHardQuad);
3265 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
3266 hasHardQuad);
3267 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
3268 hasHardQuad);
3269 case ISD::BR_CC:
3270 return LowerBR_CC(Op, DAG, *this, hasHardQuad, isV9, is64Bit);
3271 case ISD::SELECT_CC:
3272 return LowerSELECT_CC(Op, DAG, *this, hasHardQuad, isV9, is64Bit);
3273 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
3274 case ISD::VAARG: return LowerVAARG(Op, DAG);
3275 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3276 Subtarget);
3277
3278 case ISD::LOAD: return LowerLOAD(Op, DAG);
3279 case ISD::STORE: return LowerSTORE(Op, DAG);
3280 case ISD::FADD: return LowerF128Op(Op, DAG,
3281 getLibcallName(RTLIB::ADD_F128), 2);
3282 case ISD::FSUB: return LowerF128Op(Op, DAG,
3283 getLibcallName(RTLIB::SUB_F128), 2);
3284 case ISD::FMUL: return LowerF128Op(Op, DAG,
3285 getLibcallName(RTLIB::MUL_F128), 2);
3286 case ISD::FDIV: return LowerF128Op(Op, DAG,
3287 getLibcallName(RTLIB::DIV_F128), 2);
3288 case ISD::FSQRT: return LowerF128Op(Op, DAG,
3289 getLibcallName(RTLIB::SQRT_F128),1);
3290 case ISD::FABS:
3291 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3292 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
3293 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
3294 case ISD::ADDC:
3295 case ISD::ADDE:
3296 case ISD::SUBC:
3297 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
3298 case ISD::UMULO:
3299 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
3300 case ISD::ATOMIC_LOAD:
3301 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3302 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3303 }
3304 }
3305
bitcastConstantFPToInt(ConstantFPSDNode * C,const SDLoc & DL,SelectionDAG & DAG) const3306 SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
3307 const SDLoc &DL,
3308 SelectionDAG &DAG) const {
3309 APInt V = C->getValueAPF().bitcastToAPInt();
3310 SDValue Lo = DAG.getConstant(V.zextOrTrunc(32), DL, MVT::i32);
3311 SDValue Hi = DAG.getConstant(V.lshr(32).zextOrTrunc(32), DL, MVT::i32);
3312 if (DAG.getDataLayout().isLittleEndian())
3313 std::swap(Lo, Hi);
3314 return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo});
3315 }
3316
PerformBITCASTCombine(SDNode * N,DAGCombinerInfo & DCI) const3317 SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
3318 DAGCombinerInfo &DCI) const {
3319 SDLoc dl(N);
3320 SDValue Src = N->getOperand(0);
3321
3322 if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 &&
3323 Src.getSimpleValueType() == MVT::f64)
3324 return bitcastConstantFPToInt(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
3325
3326 return SDValue();
3327 }
3328
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const3329 SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N,
3330 DAGCombinerInfo &DCI) const {
3331 switch (N->getOpcode()) {
3332 default:
3333 break;
3334 case ISD::BITCAST:
3335 return PerformBITCASTCombine(N, DCI);
3336 }
3337 return SDValue();
3338 }
3339
3340 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * BB) const3341 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3342 MachineBasicBlock *BB) const {
3343 switch (MI.getOpcode()) {
3344 default: llvm_unreachable("Unknown SELECT_CC!");
3345 case SP::SELECT_CC_Int_ICC:
3346 case SP::SELECT_CC_FP_ICC:
3347 case SP::SELECT_CC_DFP_ICC:
3348 case SP::SELECT_CC_QFP_ICC:
3349 if (Subtarget->isV9())
3350 return expandSelectCC(MI, BB, SP::BPICC);
3351 return expandSelectCC(MI, BB, SP::BCOND);
3352 case SP::SELECT_CC_Int_XCC:
3353 case SP::SELECT_CC_FP_XCC:
3354 case SP::SELECT_CC_DFP_XCC:
3355 case SP::SELECT_CC_QFP_XCC:
3356 return expandSelectCC(MI, BB, SP::BPXCC);
3357 case SP::SELECT_CC_Int_FCC:
3358 case SP::SELECT_CC_FP_FCC:
3359 case SP::SELECT_CC_DFP_FCC:
3360 case SP::SELECT_CC_QFP_FCC:
3361 if (Subtarget->isV9())
3362 return expandSelectCC(MI, BB, SP::FBCOND_V9);
3363 return expandSelectCC(MI, BB, SP::FBCOND);
3364 }
3365 }
3366
3367 MachineBasicBlock *
expandSelectCC(MachineInstr & MI,MachineBasicBlock * BB,unsigned BROpcode) const3368 SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3369 unsigned BROpcode) const {
3370 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3371 DebugLoc dl = MI.getDebugLoc();
3372 unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
3373
3374 // To "insert" a SELECT_CC instruction, we actually have to insert the
3375 // triangle control-flow pattern. The incoming instruction knows the
3376 // destination vreg to set, the condition code register to branch on, the
3377 // true/false values to select between, and the condition code for the branch.
3378 //
3379 // We produce the following control flow:
3380 // ThisMBB
3381 // | \
3382 // | IfFalseMBB
3383 // | /
3384 // SinkMBB
3385 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3386 MachineFunction::iterator It = ++BB->getIterator();
3387
3388 MachineBasicBlock *ThisMBB = BB;
3389 MachineFunction *F = BB->getParent();
3390 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
3391 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3392 F->insert(It, IfFalseMBB);
3393 F->insert(It, SinkMBB);
3394
3395 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3396 SinkMBB->splice(SinkMBB->begin(), ThisMBB,
3397 std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end());
3398 SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
3399
3400 // Set the new successors for ThisMBB.
3401 ThisMBB->addSuccessor(IfFalseMBB);
3402 ThisMBB->addSuccessor(SinkMBB);
3403
3404 BuildMI(ThisMBB, dl, TII.get(BROpcode))
3405 .addMBB(SinkMBB)
3406 .addImm(CC);
3407
3408 // IfFalseMBB just falls through to SinkMBB.
3409 IfFalseMBB->addSuccessor(SinkMBB);
3410
3411 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3412 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
3413 MI.getOperand(0).getReg())
3414 .addReg(MI.getOperand(1).getReg())
3415 .addMBB(ThisMBB)
3416 .addReg(MI.getOperand(2).getReg())
3417 .addMBB(IfFalseMBB);
3418
3419 MI.eraseFromParent(); // The pseudo instruction is gone now.
3420 return SinkMBB;
3421 }
3422
3423 //===----------------------------------------------------------------------===//
3424 // Sparc Inline Assembly Support
3425 //===----------------------------------------------------------------------===//
3426
3427 /// getConstraintType - Given a constraint letter, return the type of
3428 /// constraint it is for this target.
3429 SparcTargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const3430 SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3431 if (Constraint.size() == 1) {
3432 switch (Constraint[0]) {
3433 default: break;
3434 case 'r':
3435 case 'f':
3436 case 'e':
3437 return C_RegisterClass;
3438 case 'I': // SIMM13
3439 return C_Immediate;
3440 }
3441 }
3442
3443 return TargetLowering::getConstraintType(Constraint);
3444 }
3445
3446 TargetLowering::ConstraintWeight SparcTargetLowering::
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const3447 getSingleConstraintMatchWeight(AsmOperandInfo &info,
3448 const char *constraint) const {
3449 ConstraintWeight weight = CW_Invalid;
3450 Value *CallOperandVal = info.CallOperandVal;
3451 // If we don't have a value, we can't do a match,
3452 // but allow it at the lowest weight.
3453 if (!CallOperandVal)
3454 return CW_Default;
3455
3456 // Look at the constraint type.
3457 switch (*constraint) {
3458 default:
3459 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3460 break;
3461 case 'I': // SIMM13
3462 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3463 if (isInt<13>(C->getSExtValue()))
3464 weight = CW_Constant;
3465 }
3466 break;
3467 }
3468 return weight;
3469 }
3470
3471 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3472 /// vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint(SDValue Op,StringRef Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const3473 void SparcTargetLowering::LowerAsmOperandForConstraint(
3474 SDValue Op, StringRef Constraint, std::vector<SDValue> &Ops,
3475 SelectionDAG &DAG) const {
3476 SDValue Result;
3477
3478 // Only support length 1 constraints for now.
3479 if (Constraint.size() > 1)
3480 return;
3481
3482 char ConstraintLetter = Constraint[0];
3483 switch (ConstraintLetter) {
3484 default: break;
3485 case 'I':
3486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3487 if (isInt<13>(C->getSExtValue())) {
3488 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3489 Op.getValueType());
3490 break;
3491 }
3492 return;
3493 }
3494 }
3495
3496 if (Result.getNode()) {
3497 Ops.push_back(Result);
3498 return;
3499 }
3500 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3501 }
3502
3503 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const3504 SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3505 StringRef Constraint,
3506 MVT VT) const {
3507 if (Constraint.empty())
3508 return std::make_pair(0U, nullptr);
3509
3510 if (Constraint.size() == 1) {
3511 switch (Constraint[0]) {
3512 case 'r':
3513 if (VT == MVT::v2i32)
3514 return std::make_pair(0U, &SP::IntPairRegClass);
3515 else if (Subtarget->is64Bit())
3516 return std::make_pair(0U, &SP::I64RegsRegClass);
3517 else
3518 return std::make_pair(0U, &SP::IntRegsRegClass);
3519 case 'f':
3520 if (VT == MVT::f32 || VT == MVT::i32)
3521 return std::make_pair(0U, &SP::FPRegsRegClass);
3522 else if (VT == MVT::f64 || VT == MVT::i64)
3523 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3524 else if (VT == MVT::f128)
3525 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3526 // This will generate an error message
3527 return std::make_pair(0U, nullptr);
3528 case 'e':
3529 if (VT == MVT::f32 || VT == MVT::i32)
3530 return std::make_pair(0U, &SP::FPRegsRegClass);
3531 else if (VT == MVT::f64 || VT == MVT::i64 )
3532 return std::make_pair(0U, &SP::DFPRegsRegClass);
3533 else if (VT == MVT::f128)
3534 return std::make_pair(0U, &SP::QFPRegsRegClass);
3535 // This will generate an error message
3536 return std::make_pair(0U, nullptr);
3537 }
3538 }
3539
3540 if (Constraint.front() != '{')
3541 return std::make_pair(0U, nullptr);
3542
3543 assert(Constraint.back() == '}' && "Not a brace enclosed constraint?");
3544 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2);
3545 if (RegName.empty())
3546 return std::make_pair(0U, nullptr);
3547
3548 unsigned long long RegNo;
3549 // Handle numbered register aliases.
3550 if (RegName[0] == 'r' &&
3551 getAsUnsignedInteger(RegName.begin() + 1, 10, RegNo)) {
3552 // r0-r7 -> g0-g7
3553 // r8-r15 -> o0-o7
3554 // r16-r23 -> l0-l7
3555 // r24-r31 -> i0-i7
3556 if (RegNo > 31)
3557 return std::make_pair(0U, nullptr);
3558 const char RegTypes[] = {'g', 'o', 'l', 'i'};
3559 char RegType = RegTypes[RegNo / 8];
3560 char RegIndex = '0' + (RegNo % 8);
3561 char Tmp[] = {'{', RegType, RegIndex, '}', 0};
3562 return getRegForInlineAsmConstraint(TRI, Tmp, VT);
3563 }
3564
3565 // Rewrite the fN constraint according to the value type if needed.
3566 if (VT != MVT::f32 && VT != MVT::Other && RegName[0] == 'f' &&
3567 getAsUnsignedInteger(RegName.begin() + 1, 10, RegNo)) {
3568 if (VT == MVT::f64 && (RegNo % 2 == 0)) {
3569 return getRegForInlineAsmConstraint(
3570 TRI, StringRef("{d" + utostr(RegNo / 2) + "}"), VT);
3571 } else if (VT == MVT::f128 && (RegNo % 4 == 0)) {
3572 return getRegForInlineAsmConstraint(
3573 TRI, StringRef("{q" + utostr(RegNo / 4) + "}"), VT);
3574 } else {
3575 return std::make_pair(0U, nullptr);
3576 }
3577 }
3578
3579 auto ResultPair =
3580 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3581 if (!ResultPair.second)
3582 return std::make_pair(0U, nullptr);
3583
3584 // Force the use of I64Regs over IntRegs for 64-bit values.
3585 if (Subtarget->is64Bit() && VT == MVT::i64) {
3586 assert(ResultPair.second == &SP::IntRegsRegClass &&
3587 "Unexpected register class");
3588 return std::make_pair(ResultPair.first, &SP::I64RegsRegClass);
3589 }
3590
3591 return ResultPair;
3592 }
3593
3594 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const3595 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3596 // The Sparc target isn't yet aware of offsets.
3597 return false;
3598 }
3599
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const3600 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3601 SmallVectorImpl<SDValue>& Results,
3602 SelectionDAG &DAG) const {
3603
3604 SDLoc dl(N);
3605
3606 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3607
3608 switch (N->getOpcode()) {
3609 default:
3610 llvm_unreachable("Do not know how to custom type legalize this operation!");
3611
3612 case ISD::FP_TO_SINT:
3613 case ISD::FP_TO_UINT:
3614 // Custom lower only if it involves f128 or i64.
3615 if (N->getOperand(0).getValueType() != MVT::f128
3616 || N->getValueType(0) != MVT::i64)
3617 return;
3618 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3619 ? RTLIB::FPTOSINT_F128_I64
3620 : RTLIB::FPTOUINT_F128_I64);
3621
3622 Results.push_back(LowerF128Op(SDValue(N, 0),
3623 DAG,
3624 getLibcallName(libCall),
3625 1));
3626 return;
3627 case ISD::READCYCLECOUNTER: {
3628 assert(Subtarget->hasLeonCycleCounter());
3629 SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32);
3630 SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32);
3631 SDValue Ops[] = { Lo, Hi };
3632 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops);
3633 Results.push_back(Pair);
3634 Results.push_back(N->getOperand(0));
3635 return;
3636 }
3637 case ISD::SINT_TO_FP:
3638 case ISD::UINT_TO_FP:
3639 // Custom lower only if it involves f128 or i64.
3640 if (N->getValueType(0) != MVT::f128
3641 || N->getOperand(0).getValueType() != MVT::i64)
3642 return;
3643
3644 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3645 ? RTLIB::SINTTOFP_I64_F128
3646 : RTLIB::UINTTOFP_I64_F128);
3647
3648 Results.push_back(LowerF128Op(SDValue(N, 0),
3649 DAG,
3650 getLibcallName(libCall),
3651 1));
3652 return;
3653 case ISD::LOAD: {
3654 LoadSDNode *Ld = cast<LoadSDNode>(N);
3655 // Custom handling only for i64: turn i64 load into a v2i32 load,
3656 // and a bitcast.
3657 if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3658 return;
3659
3660 SDLoc dl(N);
3661 SDValue LoadRes = DAG.getExtLoad(
3662 Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(),
3663 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32,
3664 Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags(),
3665 Ld->getAAInfo());
3666
3667 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
3668 Results.push_back(Res);
3669 Results.push_back(LoadRes.getValue(1));
3670 return;
3671 }
3672 }
3673 }
3674
3675 // Override to enable LOAD_STACK_GUARD lowering on Linux.
useLoadStackGuardNode() const3676 bool SparcTargetLowering::useLoadStackGuardNode() const {
3677 if (!Subtarget->isTargetLinux())
3678 return TargetLowering::useLoadStackGuardNode();
3679 return true;
3680 }
3681
3682 // Override to disable global variable loading on Linux.
insertSSPDeclarations(Module & M) const3683 void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
3684 if (!Subtarget->isTargetLinux())
3685 return TargetLowering::insertSSPDeclarations(M);
3686 }
3687
AdjustInstrPostInstrSelection(MachineInstr & MI,SDNode * Node) const3688 void SparcTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3689 SDNode *Node) const {
3690 assert(MI.getOpcode() == SP::SUBCCrr || MI.getOpcode() == SP::SUBCCri);
3691 // If the result is dead, replace it with %g0.
3692 if (!Node->hasAnyUseOfValue(0))
3693 MI.getOperand(0).setReg(SP::G0);
3694 }
3695