| /dports/cad/nvc/nvc-r1.5.3/test/regress/ |
| H A D | issue111.vhd | 4 D : out bit port
8 architecture rtl of t1 is architecture
16 D : out bit_vector(7 downto 0) port
20 architecture rtl of test is architecture
39 signal D : bit_vector(7 downto 0); signal
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| H A D | issue112.vhd | 4 D : out bit port
8 architecture rtl of t1 is architecture
27 architecture rtl of test2 is architecture
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| H A D | issue153.vhd | 13 architecture rtl of test_inst is architecture
34 signal D :bit_vector(7 downto 0); signal
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| /dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug037/ |
| H A D | arith_addw.vhdl | 79 architecture rtl of arith_addw is architecture
205 constant D : positive := 2**(i-1); constant
225 constant D : positive := 2**(i-1); constant
239 constant D : positive := 2**(2*LEVELS-i-1); constant
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| /dports/math/oink/oink-c1259fe/src/ |
| H A D | rtl.cpp | 405 RTLSolver::rtl(bitset &SG, int only_player, int depth) in rtl() function in pg::RTLSolver
496 const auto D = dominions; in rtl() local
511 const auto D = dominions; in rtl() local
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| /dports/devel/universal-ctags/ctags-p5.9.20211128.0/Units/review-needed.r/test.vhd.t/ |
| H A D | input.vhd | 121 architecture rtl of AND2 is architecture
239 architecture rtl of BIDIR is architecture
1489 architecture rtl of DFF is architecture
1513 architecture rtl of DFF is architecture
1537 architecture rtl of DFF is architecture
1565 architecture rtl of DFF is architecture
1589 architecture rtl of DFF is architecture
1613 architecture rtl of DFF is architecture
2409 D, Clk: in std_logic; port
6304 port (D, Clk: in std_logic; port in simPrimitives.SimDFF
[all …]
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| /dports/devel/geany-legacy/geany-1.37.1/tests/ctags/ |
| H A D | test.vhd | 121 architecture rtl of AND2 is architecture
239 architecture rtl of BIDIR is architecture
1489 architecture rtl of DFF is architecture
1513 architecture rtl of DFF is architecture
1537 architecture rtl of DFF is architecture
1565 architecture rtl of DFF is architecture
1589 architecture rtl of DFF is architecture
1613 architecture rtl of DFF is architecture
2409 D, Clk: in std_logic; port
6304 port (D, Clk: in std_logic; port in simPrimitives.SimDFF
[all …]
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| /dports/devel/geany/geany-1.38/tests/ctags/ |
| H A D | test.vhd | 121 architecture rtl of AND2 is architecture
239 architecture rtl of BIDIR is architecture
1489 architecture rtl of DFF is architecture
1513 architecture rtl of DFF is architecture
1537 architecture rtl of DFF is architecture
1565 architecture rtl of DFF is architecture
1589 architecture rtl of DFF is architecture
1613 architecture rtl of DFF is architecture
2409 D, Clk: in std_logic; port
6304 port (D, Clk: in std_logic; port in simPrimitives.SimDFF
[all …]
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| /dports/science/madness/madness-ebb3fd7/src/madness/external/elemental/external/pmrrr/src/ |
| H A D | plarre.c | 123 double *restrict D = Dstruct->D; in plarre() local
412 int n, double *D, double *E, double *E2, in eigval_approx_proc()
549 int n, double *D, double *E, double *E2, in eigval_root_proc()
560 double rtl; in eigval_root_proc() local
738 int n, double *D, double *E, double *E2, in eigval_refine_proc()
904 double *D, *E, *E2, *gersch; in eigval_subset_thread_a() local
969 auxarg1_t *create_auxarg1(int n, double *D, double *E, double *E2, in create_auxarg1()
1005 void retrieve_auxarg1(auxarg1_t *arg, int *n, double **D, double **E, in retrieve_auxarg1()
1041 double *D, *DE2; in eigval_subset_thread_r() local
1088 auxarg2_t *create_auxarg2(int bl_size, double *D, double *DE2, in create_auxarg2()
[all …]
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| /dports/lang/gcc6-aux/gcc-6-20180516/gcc/config/rl78/ |
| H A D | rl78.c | 2584 #define D gen_rtx_REG (QImode, D_REG) macro
4328 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/lang/gnat_util/gcc-6-20180516/gcc/config/rl78/ |
| H A D | rl78.c | 2584 #define D gen_rtx_REG (QImode, D_REG) macro
4328 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/devel/arm-none-eabi-gcc492/gcc-4.9.2/gcc/config/arm/ |
| H A D | arm.c | 22886 #define VAR4(T, N, A, B, C, D) \ argument
22889 #define VAR5(T, N, A, B, C, D, E) \ argument
22892 #define VAR6(T, N, A, B, C, D, E, F) \ argument
22895 #define VAR7(T, N, A, B, C, D, E, F, G) \ argument
22898 #define VAR8(T, N, A, B, C, D, E, F, G, H) \ argument
22943 #define VAR4(T, N, A, B, C, D) \ argument
22946 #define VAR5(T, N, A, B, C, D, E) \ argument
22949 #define VAR6(T, N, A, B, C, D, E, F) \ argument
22952 #define VAR7(T, N, A, B, C, D, E, F, G) \ argument
28052 arm_encode_section_info (tree decl, rtx rtl, int first) in arm_encode_section_info()
[all …]
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| /dports/devel/aarch64-none-elf-gcc/gcc-8.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/lang/gcc9/gcc-9.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2802 #define D gen_rtx_REG (QImode, D_REG) macro
4553 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/devel/avr-gcc/gcc-10.2.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/devel/riscv64-gcc/gcc-8.3.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/lang/gcc11-devel/gcc-11-20211009/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/lang/gcc12-devel/gcc-12-20211205/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4541 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/devel/riscv32-unknown-elf-gcc/gcc-8.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/devel/arm-none-eabi-gcc/gcc-8.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
|
| /dports/devel/riscv64-none-elf-gcc/gcc-8.4.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/misc/cxx_atomics_pic/gcc-11.2.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/lang/gcc9-aux/gcc-9.1.0/gcc/config/rl78/ |
| H A D | rl78.c | 2802 #define D gen_rtx_REG (QImode, D_REG) macro
4553 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/lang/gcc10/gcc-10.3.0/gcc/config/rl78/ |
| H A D | rl78.c | 2791 #define D gen_rtx_REG (QImode, D_REG) macro
4542 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
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| /dports/lang/gcc9-devel/gcc-9-20211007/gcc/config/rl78/ |
| H A D | rl78.c | 2802 #define D gen_rtx_REG (QImode, D_REG) macro
4553 rl78_encode_section_info (tree decl, rtx rtl, int first) in rl78_encode_section_info()
|