1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GT_REGS_H_ 7 #define _XE_GT_REGS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 /* 12 * The GSI register range [0x0 - 0x40000) is replicated at a higher offset 13 * for the media GT. xe_mmio and xe_gt_mcr functions will automatically 14 * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT. 15 */ 16 #define MEDIA_GT_GSI_OFFSET 0x380000 17 #define MEDIA_GT_GSI_LENGTH 0x40000 18 19 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ 20 #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) 21 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 22 #define MTL_CC_MASK REG_GENMASK(12, 9) 23 24 /* RPM unit config (Gen8+) */ 25 #define RPM_CONFIG0 XE_REG(0xd00) 26 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) 27 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 28 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 29 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 30 #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 31 #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 32 33 #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4) 34 #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4) 35 #define FORCEWAKE_ACK_RENDER XE_REG(0xd84) 36 37 #define GMD_ID XE_REG(0xd8c) 38 #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 39 #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 40 #define GMD_ID_REVID REG_GENMASK(5, 0) 41 42 #define FORCEWAKE_ACK_GSC XE_REG(0xdf8) 43 #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc) 44 45 #define MCFG_MCR_SELECTOR XE_REG(0xfd0) 46 #define MTL_MCR_SELECTOR XE_REG(0xfd4) 47 #define SF_MCR_SELECTOR XE_REG(0xfd8) 48 #define MCR_SELECTOR XE_REG(0xfdc) 49 #define GAM_MCR_SELECTOR XE_REG(0xfe0) 50 #define MCR_MULTICAST REG_BIT(31) 51 #define MCR_SLICE_MASK REG_GENMASK(30, 27) 52 #define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice) 53 #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24) 54 #define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice) 55 #define MTL_MCR_GROUPID REG_GENMASK(11, 8) 56 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) 57 58 #define PS_INVOCATION_COUNT XE_REG(0x2348) 59 60 #define XELP_GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4) 61 #define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4) 62 #define CCS_AUX_INV XE_REG(0x4208) 63 64 #define VD0_AUX_INV XE_REG(0x4218) 65 #define VE0_AUX_INV XE_REG(0x4238) 66 67 #define VE1_AUX_INV XE_REG(0x42b8) 68 #define AUX_INV REG_BIT(0) 69 70 #define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4) 71 #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910) 72 #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8) 73 74 #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED) 75 #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10) 76 77 #define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED) 78 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) 79 80 #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED) 81 #define TBIMR_FAST_CLIP REG_BIT(5) 82 83 #define FF_MODE XE_REG_MCR(0x6210) 84 #define DIS_TE_AUTOSTRIP REG_BIT(31) 85 #define DIS_MESH_PARTIAL_AUTOSTRIP REG_BIT(16) 86 #define DIS_MESH_AUTOSTRIP REG_BIT(15) 87 88 #define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED) 89 #define DIS_PARTIAL_AUTOSTRIP REG_BIT(9) 90 #define DIS_AUTOSTRIP REG_BIT(6) 91 #define DIS_OVER_FETCH_CACHE REG_BIT(1) 92 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) 93 94 #define FF_MODE2 XE_REG(0x6604) 95 #define XEHP_FF_MODE2 XE_REG_MCR(0x6604) 96 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 97 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 98 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 99 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 100 101 #define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED) 102 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 103 104 #define COMMON_SLICE_CHICKEN1 XE_REG(0x7010, XE_REG_OPTION_MASKED) 105 #define DISABLE_BOTTOM_CLIP_RECTANGLE_TEST REG_BIT(14) 106 107 #define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) 108 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) 109 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) 110 111 #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED) 112 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 113 114 #define XEHP_PSS_CHICKEN XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED) 115 #define FLSH_IGNORES_PSD REG_BIT(10) 116 #define FD_END_COLLECT REG_BIT(5) 117 118 #define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED) 119 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) 120 121 #define COMMON_SLICE_CHICKEN3 XE_REG(0x7304, XE_REG_OPTION_MASKED) 122 #define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED) 123 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) 124 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) 125 #define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) 126 #define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) 127 128 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED) 129 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 130 131 #define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED) 132 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) 133 134 #define VF_SCRATCHPAD XE_REG(0x83a8, XE_REG_OPTION_MASKED) 135 #define XE2_VFG_TED_CREDIT_INTERFACE_DISABLE REG_BIT(13) 136 137 #define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4, XE_REG_OPTION_MASKED) 138 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) 139 140 #define SQCNT1 XE_REG_MCR(0x8718) 141 #define XELPMP_SQCNT1 XE_REG(0x8718) 142 #define ENFORCE_RAR REG_BIT(23) 143 144 #define XEHP_SQCM XE_REG_MCR(0x8724) 145 #define EN_32B_ACCESS REG_BIT(30) 146 147 #define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800) 148 #define XE2_FLAT_CCS_ENABLE REG_BIT(0) 149 #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6) 150 151 #define XE2_FLAT_CCS_BASE_RANGE_UPPER XE_REG_MCR(0x8804) 152 #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0) 153 154 #define GSCPSMI_BASE XE_REG(0x880c) 155 156 #define CCCHKNREG1 XE_REG_MCR(0x8828) 157 #define ENCOMPPERFFIX REG_BIT(18) 158 159 /* Fuse readout registers for GT */ 160 #define XEHP_FUSE4 XE_REG(0x9114) 161 #define CFEG_WMTP_DISABLE REG_BIT(20) 162 #define CCS_EN_MASK REG_GENMASK(19, 16) 163 #define GT_L3_EXC_MASK REG_GENMASK(6, 4) 164 165 #define MIRROR_FUSE3 XE_REG(0x9118) 166 #define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16) 167 #define L3BANK_PAIR_COUNT 4 168 #define XEHPC_GT_L3_MODE_MASK REG_GENMASK(7, 4) 169 #define XE2_GT_L3_MODE_MASK REG_GENMASK(7, 4) 170 #define L3BANK_MASK REG_GENMASK(3, 0) 171 #define XELP_GT_L3_MODE_MASK REG_GENMASK(7, 0) 172 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 173 #define MAX_MSLICES 4 174 #define MEML3_EN_MASK REG_GENMASK(3, 0) 175 176 #define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ 177 #define XELP_EU_MASK REG_GENMASK(7, 0) 178 #define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c) 179 180 #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140) 181 #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) 182 #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) 183 184 #define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144) 185 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148) 186 #define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c) 187 #define XE2_GT_GEOMETRY_DSS_1 XE_REG(0x9150) 188 #define XE2_GT_GEOMETRY_DSS_2 XE_REG(0x9154) 189 190 #define GDRST XE_REG(0x941c) 191 #define GRDOM_GUC REG_BIT(3) 192 #define GRDOM_FULL REG_BIT(0) 193 194 #define MISCCPCTL XE_REG(0x9424) 195 #define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) 196 197 #define UNSLCGCTL9430 XE_REG(0x9430) 198 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) 199 200 #define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434) 201 #define VFUNIT_CLKGATE_DIS REG_BIT(20) 202 #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ 203 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ 204 #define GAMEDIA_CLKGATE_DIS REG_BIT(11) 205 #define HSUNIT_CLKGATE_DIS REG_BIT(8) 206 #define VSUNIT_CLKGATE_DIS REG_BIT(3) 207 208 #define UNSLCGCTL9440 XE_REG(0x9440) 209 #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) 210 #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) 211 #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) 212 #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24) 213 #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23) 214 #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22) 215 #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21) 216 #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17) 217 #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16) 218 #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15) 219 #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) 220 #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) 221 222 #define UNSLCGCTL9444 XE_REG(0x9444) 223 #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) 224 #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) 225 #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) 226 #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27) 227 #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26) 228 #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25) 229 #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24) 230 #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23) 231 #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22) 232 #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21) 233 #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20) 234 #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19) 235 #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18) 236 #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17) 237 #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) 238 #define LTCDD_CLKGATE_DIS REG_BIT(10) 239 240 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4) 241 #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 242 #define L3_CLKGATE_DIS REG_BIT(16) 243 #define NODEDSS_CLKGATE_DIS REG_BIT(12) 244 #define MSCUNIT_CLKGATE_DIS REG_BIT(10) 245 #define RCCUNIT_CLKGATE_DIS REG_BIT(7) 246 #define SARBUNIT_CLKGATE_DIS REG_BIT(5) 247 #define SBEUNIT_CLKGATE_DIS REG_BIT(4) 248 249 #define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4) 250 #define VSUNIT_CLKGATE2_DIS REG_BIT(19) 251 252 #define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524) 253 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) 254 #define GWUNIT_CLKGATE_DIS REG_BIT(16) 255 256 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528) 257 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 258 259 #define SSMCGCTL9530 XE_REG_MCR(0x9530) 260 #define RTFUNIT_CLKGATE_DIS REG_BIT(18) 261 262 #define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550) 263 #define DFR_DISABLE REG_BIT(9) 264 265 #define RPNSWREQ XE_REG(0xa008) 266 #define REQ_RATIO_MASK REG_GENMASK(31, 23) 267 268 #define RP_CONTROL XE_REG(0xa024) 269 #define RPSWCTL_MASK REG_GENMASK(10, 9) 270 #define RPSWCTL_ENABLE REG_FIELD_PREP(RPSWCTL_MASK, 2) 271 #define RPSWCTL_DISABLE REG_FIELD_PREP(RPSWCTL_MASK, 0) 272 #define RC_CONTROL XE_REG(0xa090) 273 #define RC_CTL_HW_ENABLE REG_BIT(31) 274 #define RC_CTL_TO_MODE REG_BIT(28) 275 #define RC_CTL_RC6_ENABLE REG_BIT(18) 276 #define RC_STATE XE_REG(0xa094) 277 #define RC_IDLE_HYSTERSIS XE_REG(0xa0ac) 278 279 #define PMINTRMSK XE_REG(0xa168) 280 #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31) 281 #define ARAT_EXPIRED_INTRMSK REG_BIT(9) 282 283 #define FORCEWAKE_GT XE_REG(0xa188) 284 285 #define PG_ENABLE XE_REG(0xa210) 286 #define VD2_MFXVDENC_POWERGATE_ENABLE REG_BIT(8) 287 #define VD2_HCP_POWERGATE_ENABLE REG_BIT(7) 288 #define VD0_MFXVDENC_POWERGATE_ENABLE REG_BIT(4) 289 #define VD0_HCP_POWERGATE_ENABLE REG_BIT(3) 290 291 #define CTC_MODE XE_REG(0xa26c) 292 #define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 293 #define CTC_SOURCE_DIVIDE_LOGIC REG_BIT(0) 294 295 #define FORCEWAKE_RENDER XE_REG(0xa278) 296 #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4) 297 #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4) 298 #define FORCEWAKE_GSC XE_REG(0xa618) 299 300 #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED) 301 #define XEHPC_OVRLSCCC REG_BIT(0) 302 303 /* L3 Cache Control */ 304 #define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4) 305 #define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4) 306 #define LNCFCMOCS_REG_COUNT 32 307 308 #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4) 309 #define XEHP_LNESPARE REG_BIT(19) 310 311 #define L3SQCREG3 XE_REG_MCR(0xb108) 312 #define COMPPWOVERFETCHEN REG_BIT(28) 313 314 #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158) 315 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) 316 317 #define XEHP_L3SCQREG7 XE_REG_MCR(0xb188) 318 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) 319 320 #define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8) 321 322 #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) 323 324 #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) 325 #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) 326 #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) 327 #define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34) 328 #define XELPMP_VDBX_MOD_CTRL XE_REG(0xcf34) 329 #define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38) 330 #define XELPMP_VEBX_MOD_CTRL XE_REG(0xcf38) 331 #define FORCE_MISS_FTLB REG_BIT(3) 332 333 #define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c) 334 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) 335 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) 336 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) 337 338 #define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54) 339 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) 340 #define GLOBAL_INVALIDATION_MODE REG_BIT(2) 341 342 #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED) 343 #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0) 344 345 #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED) 346 #define ENABLE_SMALLPL REG_BIT(15) 347 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) 348 #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 349 #define INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) 350 351 #define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED) 352 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) 353 354 #define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED) 355 #define DISABLE_ECC REG_BIT(5) 356 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) 357 358 #define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED) 359 #define DISABLE_GRF_CLEAR REG_BIT(13) 360 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) 361 #define DISABLE_TDL_PUSH REG_BIT(9) 362 #define DIS_PICK_2ND_EU REG_BIT(7) 363 #define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) 364 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) 365 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) 366 367 #define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED) 368 #define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14) 369 #define DIS_FIX_EOT1_FLUSH REG_BIT(9) 370 371 #define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED) 372 #define SLM_WMTP_RESTORE REG_BIT(11) 373 374 #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED) 375 #define UGM_BACKUP_MODE REG_BIT(13) 376 #define MDQ_ARBITRATION_MODE REG_BIT(12) 377 #define EARLY_EOT_DIS REG_BIT(1) 378 379 #define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED) 380 #define DISABLE_READ_SUPPRESSION REG_BIT(15) 381 #define DISABLE_EARLY_READ REG_BIT(14) 382 #define ENABLE_LARGE_GRF_MODE REG_BIT(12) 383 #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 384 #define DISABLE_TDL_SVHS_GATING REG_BIT(1) 385 #define DISABLE_DOP_GATING REG_BIT(0) 386 387 #define RT_CTRL XE_REG_MCR(0xe530) 388 #define DIS_NULL_QUERY REG_BIT(10) 389 390 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534) 391 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31) 392 393 #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) 394 #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) 395 #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) 396 397 #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) 398 #define DISABLE_D8_D16_COASLESCE REG_BIT(30) 399 #define WR_REQ_CHAINING_DIS REG_BIT(26) 400 #define TGM_WRITE_EOM_FORCE REG_BIT(17) 401 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) 402 #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13) 403 404 #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) 405 #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) 406 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) 407 #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32) 408 #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32) 409 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 410 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 411 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 412 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 413 414 #define SARB_CHICKEN1 XE_REG_MCR(0xe90c) 415 #define COMP_CKN_IN REG_GENMASK(30, 29) 416 417 #define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED) 418 #define RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) 419 #define RCU_MODE_CCS_ENABLE REG_BIT(0) 420 421 /* 422 * Total of 4 cslices, where each cslice is in the form: 423 * [0-3] CCS ID 424 * [4-6] RSVD 425 * [7] Disabled 426 */ 427 #define CCS_MODE XE_REG(0x14804) 428 #define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */ 429 #define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */ 430 #define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1) 431 #define CCS_MODE_CSLICE(cslice, ccs) \ 432 ((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH)) 433 434 #define FORCEWAKE_ACK_GT XE_REG(0x130044) 435 #define FORCEWAKE_KERNEL BIT(0) 436 #define FORCEWAKE_USER BIT(1) 437 #define FORCEWAKE_KERNEL_FALLBACK BIT(15) 438 439 #define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030) 440 #define MTL_MEDIA_MC6 XE_REG(0x138048) 441 442 #define GT_CORE_STATUS XE_REG(0x138060) 443 #define RCN_MASK REG_GENMASK(2, 0) 444 #define GT_C0 0 445 #define GT_C6 3 446 447 #define GT_GFX_RC6_LOCKED XE_REG(0x138104) 448 #define GT_GFX_RC6 XE_REG(0x138108) 449 450 #define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8) 451 #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 452 #define PROCHOT_MASK REG_BIT(0) 453 #define THERMAL_LIMIT_MASK REG_BIT(1) 454 #define RATL_MASK REG_BIT(5) 455 #define VR_THERMALERT_MASK REG_BIT(6) 456 #define VR_TDC_MASK REG_BIT(7) 457 #define POWER_LIMIT_4_MASK REG_BIT(8) 458 #define POWER_LIMIT_1_MASK REG_BIT(10) 459 #define POWER_LIMIT_2_MASK REG_BIT(11) 460 461 #define GT_PERF_STATUS XE_REG(0x1381b4) 462 #define VOLTAGE_MASK REG_GENMASK(10, 0) 463 464 /* 465 * Note: Interrupt registers 1900xx are VF accessible only until version 12.50. 466 * On newer platforms, VFs are using memory-based interrupts instead. 467 * However, for simplicity we keep this XE_REG_OPTION_VF tag intact. 468 */ 469 470 #define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF) 471 #define INTR_GSC REG_BIT(31) 472 #define INTR_GUC REG_BIT(25) 473 #define INTR_MGUC REG_BIT(24) 474 #define INTR_BCS8 REG_BIT(23) 475 #define INTR_BCS(x) REG_BIT(15 - (x)) 476 #define INTR_CCS(x) REG_BIT(4 + (x)) 477 #define INTR_RCS0 REG_BIT(0) 478 #define INTR_VECS(x) REG_BIT(31 - (x)) 479 #define INTR_VCS(x) REG_BIT(x) 480 481 #define RENDER_COPY_INTR_ENABLE XE_REG(0x190030, XE_REG_OPTION_VF) 482 #define VCS_VECS_INTR_ENABLE XE_REG(0x190034, XE_REG_OPTION_VF) 483 #define GUC_SG_INTR_ENABLE XE_REG(0x190038, XE_REG_OPTION_VF) 484 #define ENGINE1_MASK REG_GENMASK(31, 16) 485 #define ENGINE0_MASK REG_GENMASK(15, 0) 486 #define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c, XE_REG_OPTION_VF) 487 #define GUNIT_GSC_INTR_ENABLE XE_REG(0x190044, XE_REG_OPTION_VF) 488 #define CCS_RSVD_INTR_ENABLE XE_REG(0x190048, XE_REG_OPTION_VF) 489 490 #define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF) 491 #define INTR_DATA_VALID REG_BIT(31) 492 #define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x) 493 #define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x) 494 #define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x) 495 #define OTHER_GUC_INSTANCE 0 496 #define OTHER_GSC_HECI2_INSTANCE 3 497 #define OTHER_GSC_INSTANCE 6 498 499 #define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF) 500 #define RCS0_RSVD_INTR_MASK XE_REG(0x190090, XE_REG_OPTION_VF) 501 #define BCS_RSVD_INTR_MASK XE_REG(0x1900a0, XE_REG_OPTION_VF) 502 #define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8, XE_REG_OPTION_VF) 503 #define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac, XE_REG_OPTION_VF) 504 #define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0, XE_REG_OPTION_VF) 505 #define HECI2_RSVD_INTR_MASK XE_REG(0x1900e4) 506 #define GUC_SG_INTR_MASK XE_REG(0x1900e8, XE_REG_OPTION_VF) 507 #define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec, XE_REG_OPTION_VF) 508 #define GUNIT_GSC_INTR_MASK XE_REG(0x1900f4, XE_REG_OPTION_VF) 509 #define CCS0_CCS1_INTR_MASK XE_REG(0x190100) 510 #define CCS2_CCS3_INTR_MASK XE_REG(0x190104) 511 #define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110) 512 #define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114) 513 #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118) 514 #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c) 515 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) 516 #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) 517 #define GSC_ER_COMPLETE REG_BIT(5) 518 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4) 519 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 520 #define GT_RENDER_USER_INTERRUPT REG_BIT(0) 521 522 #endif 523