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Searched defs:LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT (Results 1 – 7 of 7) sorted by path

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_sh_mask.h3114 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
H A Ddce_11_0_sh_mask.h3184 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
H A Ddce_11_2_sh_mask.h3432 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
H A Ddce_12_0_sh_mask.h9252 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro
H A Ddce_6_0_sh_mask.h7605 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 macro
H A Ddce_8_0_sh_mask.h3192 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x11 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h40001 #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT … macro