| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 2548 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
2632 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
2764 unsigned LaneIdx = 1; in selectUnmergeValues() local
3495 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
3546 unsigned LaneIdx = VRegAndVal->Value; in selectInsertElt() local
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| H A D | AArch64ISelDAGToDAG.cpp | 482 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
506 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
526 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
569 int LaneIdx; in tryMULLV64LaneV128() local
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| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 1704 unsigned LaneIdx = Offset / 64; in select() local
2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
2986 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
3119 unsigned LaneIdx = 1; in selectUnmergeValues() local
3866 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
3917 unsigned LaneIdx = VRegAndVal->Value; in selectInsertElt() local
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| H A D | AArch64ISelDAGToDAG.cpp | 539 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
563 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
583 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
626 int LaneIdx; in tryMULLV64LaneV128() local
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| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 1704 unsigned LaneIdx = Offset / 64; in select() local
2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
2986 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
3119 unsigned LaneIdx = 1; in selectUnmergeValues() local
3866 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
3917 unsigned LaneIdx = VRegAndVal->Value; in selectInsertElt() local
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| H A D | AArch64ISelDAGToDAG.cpp | 539 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
563 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
583 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
626 int LaneIdx; in tryMULLV64LaneV128() local
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| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstructionSelector.cpp | 1704 unsigned LaneIdx = Offset / 64; in select() local
2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
2986 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
3119 unsigned LaneIdx = 1; in selectUnmergeValues() local
3866 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
3917 unsigned LaneIdx = VRegAndVal->Value; in selectInsertElt() local
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| H A D | AArch64ISelDAGToDAG.cpp | 539 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
563 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
583 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
626 int LaneIdx; in tryMULLV64LaneV128() local
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| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2204 unsigned LaneIdx = Offset / 64; in select() local
3475 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3559 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
3692 unsigned LaneIdx = 1; in selectUnmergeValues() local
4411 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4462 unsigned LaneIdx = VRegAndVal->Value; in selectInsertElt() local
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| H A D | AArch64PostLegalizerLowering.cpp | 560 auto LaneIdx = getSplatIndex(MI); in matchDupLane() local
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2125 unsigned LaneIdx = Offset / 64; in select() local
3375 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3459 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
3592 unsigned LaneIdx = 1; in selectUnmergeValues() local
4387 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4438 unsigned LaneIdx = VRegAndVal->Value; in selectInsertElt() local
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| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2451 unsigned LaneIdx = Offset / 64; in select() local
3701 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3785 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
3918 unsigned LaneIdx = 1; in selectUnmergeValues() local
4660 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4711 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
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| H A D | AArch64PostLegalizerLowering.cpp | 559 auto LaneIdx = getSplatIndex(MI); in matchDupLane() local
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2126 unsigned LaneIdx = Offset / 64; in select() local
3376 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3460 unsigned LaneIdx = VRegAndVal->Value; in selectExtractElt() local
3593 unsigned LaneIdx = 1; in selectUnmergeValues() local
4388 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4439 unsigned LaneIdx = VRegAndVal->Value; in selectInsertElt() local
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2451 unsigned LaneIdx = Offset / 64; in select() local
3701 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3785 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
3918 unsigned LaneIdx = 1; in selectUnmergeValues() local
4660 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4711 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
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| H A D | AArch64PostLegalizerLowering.cpp | 559 auto LaneIdx = getSplatIndex(MI); in matchDupLane() local
|
| /dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 469 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
493 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
513 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
556 int LaneIdx; in tryMULLV64LaneV128() local
|
| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2594 unsigned LaneIdx = Offset / 64; in select() local
3872 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3956 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
4091 unsigned LaneIdx = 1; in selectUnmergeValues() local
4774 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4825 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2594 unsigned LaneIdx = Offset / 64; in select() local
3872 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3956 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
4091 unsigned LaneIdx = 1; in selectUnmergeValues() local
4774 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4825 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2594 unsigned LaneIdx = Offset / 64; in select() local
3872 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3956 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
4091 unsigned LaneIdx = 1; in selectUnmergeValues() local
4774 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4825 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2610 unsigned LaneIdx = Offset / 64; in select() local
3940 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
4024 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
4159 unsigned LaneIdx = 1; in selectUnmergeValues() local
4849 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4965 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2594 unsigned LaneIdx = Offset / 64; in select() local
3872 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3956 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
4091 unsigned LaneIdx = 1; in selectUnmergeValues() local
4774 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4825 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2594 unsigned LaneIdx = Offset / 64; in select() local
3872 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
3956 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectExtractElt() local
4091 unsigned LaneIdx = 1; in selectUnmergeValues() local
4774 unsigned LaneIdx, const RegisterBank &RB, in emitLaneInsert()
4825 unsigned LaneIdx = VRegAndVal->Value.getSExtValue(); in selectInsertElt() local
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 594 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
618 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
638 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
681 int LaneIdx; in tryMULLV64LaneV128() local
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| /dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 593 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) { in checkHighLaneIndex()
617 SDValue &LaneOp, int &LaneIdx) { in checkV64LaneV128()
637 int LaneIdx = -1; // Will hold the lane index. in tryMLAV64LaneV128() local
680 int LaneIdx; in tryMULLV64LaneV128() local
|