| /dports/misc/rump/buildrump.sh-b914579/src/sys/dev/spi/ |
| H A D | mcp23s17.h | 47 #define MCP23x17_IODIR(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x0, PORT) argument
50 #define MCP23x17_IPOL(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x1, PORT) argument
53 #define MCP23x17_GPINTEN(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x2, PORT) argument
56 #define MCP23x17_DEFVAL(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x3, PORT) argument
59 #define MCP23x17_INTCON(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x4, PORT) argument
62 #define MCP23x17_IOCON(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x5, PORT) argument
65 #define MCP23x17_GPPU(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x6, PORT) argument
68 #define MCP23x17_INTF(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x7, PORT) argument
71 #define MCP23x17_INTCAP(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x8, PORT) argument
74 #define MCP23x17_GPIO(BANK, PORT) MCP23x17_BANKADDR(BANK, 0x9, PORT) argument
[all …]
|
| /dports/multimedia/v4l-utils/linux-5.13-rc2/arch/mips/boot/compressed/ |
| H A D | uart-16550.c | 13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) macro
18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) macro
23 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset)) macro
28 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) macro
34 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) macro
|
| /dports/multimedia/v4l_compat/linux-5.13-rc2/arch/mips/boot/compressed/ |
| H A D | uart-16550.c | 13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) macro
18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) macro
23 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset)) macro
28 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) macro
34 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) macro
|
| /dports/multimedia/libv4l/linux-5.13-rc2/arch/mips/boot/compressed/ |
| H A D | uart-16550.c | 13 #define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) macro
18 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) macro
23 #define PORT(offset) (CKSEG1ADDR(INGENIC_UART0_BASE_ADDR) + (4 * offset)) macro
28 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) macro
34 #define PORT(offset) (CKSEG1ADDR(UART0_BASE) + (4 * offset)) macro
|
| /dports/lang/qscheme/qscheme-0.5.1/ |
| H A D | port.h | 7 typedef struct PORT { struct
16 } PORT; argument
|
| /dports/devel/libzookeeper/apache-zookeeper-3.7.0/zookeeper-server/src/test/java/org/apache/zookeeper/test/ |
| H A D | ACLTest.java | 73 final int PORT = Integer.parseInt(HOSTPORT.split(":")[1]); in testNettyIpAuthDefault() local
104 final int PORT = Integer.parseInt(HOSTPORT.split(":")[1]); in testDisconnectedAddAuth() local
135 final int PORT = Integer.parseInt(HOSTPORT.split(":")[1]); in testAcls() local
224 final int PORT = Integer.parseInt(HOSTPORT.split(":")[1]); in testNullACL() local
265 final int PORT = Integer.parseInt(HOSTPORT.split(":")[1]); in testNullValueACL() local
|
| /dports/comms/py-pyserial/pyserial-3.5/test/ |
| H A D | run_all_tests.py | 23 PORT = 'loop://' variable
25 PORT = sys.argv[1] variable
|
| H A D | test_iolib.py | 33 PORT = 'loop://' variable
57 PORT = sys.argv[1] variable
|
| H A D | test_settings_dict.py | 18 PORT = 'loop://' variable
76 PORT = sys.argv[1] variable
|
| H A D | test_exclusive.py | 17 PORT = 'loop://' variable
55 PORT = sys.argv[1] variable
|
| H A D | test_high_load.py | 28 PORT = 'loop://' variable
72 PORT = sys.argv[1] variable
|
| H A D | test_rs485.py | 16 PORT = 'loop://' variable
63 PORT = sys.argv[1] variable
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot-sam460ex/drivers/video/ |
| H A D | bus_vcxk.c | 41 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
50 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
51 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
57 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
63 #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN; argument
64 #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN; argument
76 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
79 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
80 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot-sam460ex/drivers/video/ |
| H A D | bus_vcxk.c | 41 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
50 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
51 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
57 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
63 #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN; argument
64 #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN; argument
76 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
79 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
80 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
|
| /dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/u-boot-sam460ex/drivers/video/ |
| H A D | bus_vcxk.c | 41 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
50 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
51 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
57 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
63 #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN; argument
64 #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN; argument
76 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
79 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
80 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot-sam460ex/drivers/video/ |
| H A D | bus_vcxk.c | 41 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
50 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
51 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
57 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
63 #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN; argument
64 #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN; argument
76 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
79 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
80 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot-sam460ex/drivers/video/ |
| H A D | bus_vcxk.c | 41 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
50 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
51 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
57 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
63 #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN; argument
64 #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN; argument
76 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
79 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
80 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
|
| /dports/emulators/qemu/qemu-6.2.0/roms/u-boot-sam460ex/drivers/video/ |
| H A D | bus_vcxk.c | 41 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
50 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
51 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
57 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
63 #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN; argument
64 #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN; argument
76 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
79 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
80 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot-sam460ex/drivers/video/ |
| H A D | bus_vcxk.c | 41 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
50 #define VCXK_SET_PIN(PORT, PIN) writel(PIN, &pio->PORT.sodr); argument
51 #define VCXK_CLR_PIN(PORT, PIN) writel(PIN, &pio->PORT.codr); argument
57 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
63 #define VCXK_SET_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_SODR = PIN; argument
64 #define VCXK_CLR_PIN(PORT, PIN) ((AT91PS_PIO) PORT)->PIO_CODR = PIN; argument
76 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \ argument
79 #define VCXK_SET_PIN(PORT, PIN) PORT |= PIN; argument
80 #define VCXK_CLR_PIN(PORT, PIN) PORT &= ~PIN; argument
|
| /dports/java/eclipse/eclipse.platform.releng.aggregator-R4_16/rt.equinox.bundles/bundles/org.eclipse.equinox.console.tests/src/org/eclipse/equinox/console/telnet/ |
| H A D | TelnetServerTests.java | 36 private static final int PORT = 38888; field in TelnetServerTests
60 try (Socket socketClient = new Socket("localhost", PORT);) { in testTelnetServer() argument
101 try (Socket socketClient = new Socket("localhost", PORT);) { in testTelnetServerWithoutHost() argument
|
| /dports/lang/scheme48/scheme48-1.9.2/c/ |
| H A D | prescheme.h | 25 #define PS_READ_CHAR(PORT,RESULT,EOFP,STATUS) \ argument
37 #define PS_PEEK_CHAR(PORT,RESULT,EOFP,STATUS) \ argument
50 #define PS_READ_INTEGER(PORT,RESULT,EOFP,STATUS) \ argument
53 #define PS_WRITE_CHAR(CHAR,PORT,STATUS) \ argument
|
| /dports/sysutils/ansible/ansible-4.7.0/ansible_collections/community/general/tests/integration/targets/flatpak/files/ |
| H A D | serve.py | 24 HOST, PORT, PATH = sys.argv[1:4] variable
25 PORT = int(PORT) variable
|
| /dports/devel/pycharm-pro/pycharm-2020.2.3/plugins/python/helpers/pycharm_display/datalore/display/ |
| H A D | display_.py | 23 PORT = PORT_ENV variable
25 PORT = None variable
|
| /dports/net-p2p/go-ethereum/go-ethereum-1.10.14/vendor/golang.org/x/text/runes/ |
| H A D | cond_test.go | 23 transform.SpanningTransformer
34 func TestIn(t *testing.T) {
46 func testConditional(t *testing.T, f func(rt *unicode.RangeTable, t, f spanformer) spanformer) {
47 lower := f(unicode.Latin, toLower, toLower)
49 for i, tt := range []transformTest{{
|
| /dports/lang/rust/rustc-1.58.1-src/library/std/src/net/ |
| H A D | test.rs | 7 static PORT: AtomicUsize = AtomicUsize::new(0); variable
|